relibc: fix fenv asm — use memory operands for ldmxcsr/fldcw

This commit is contained in:
Red Bear OS
2026-07-10 08:58:25 +03:00
parent a34ffec558
commit 8d94e8d2ae
+5 -5
View File
@@ -17,11 +17,11 @@ pub type fexcept_t = c_int;
#[repr(C)]
pub struct fenv_t { pub mxcsr: u32, pub x87_cw: u16, pub x87_sw: u16, _pad: [u64; 2] }
#[inline] fn mxcsr_rd() -> u32 { let v:u32=0; unsafe{core::arch::asm!("stmxcsr {}",inout(reg)v,options(nostack,preserves_flags))};v }
#[inline] fn mxcsr_wr(v:u32) { let val=v; unsafe{core::arch::asm!("ldmxcsr {}",in(reg)val,options(nostack,preserves_flags))}; }
#[inline] fn cw_rd() -> u16 { let v:u16=0; unsafe{core::arch::asm!("fnstcw {}",inout(reg)v,options(nostack,preserves_flags))};v }
#[inline] fn cw_wr(v:u16) { let val=v; unsafe{core::arch::asm!("fldcw {}",in(reg)val,options(nostack,preserves_flags))}; }
#[inline] fn sw_rd() -> u16 { let v:u16=0; unsafe{core::arch::asm!("fnstsw {}",inout(reg)v,options(nostack,preserves_flags))};v }
#[inline] fn mxcsr_rd() -> u32 { let v:u32; unsafe{core::arch::asm!("stmxcsr {}",out(reg)v)};v }
#[inline] fn mxcsr_wr(v:u32) { let val=v; unsafe{core::arch::asm!("ldmxcsr [{}]",in(reg)&val,options(nostack))}; }
#[inline] fn cw_rd() -> u16 { let v:u16; unsafe{core::arch::asm!("fnstcw {}",out(reg)v)};v }
#[inline] fn cw_wr(v:u16) { let val=v; unsafe{core::arch::asm!("fldcw [{}]",in(reg)&val,options(nostack))}; }
#[inline] fn sw_rd() -> u16 { let v:u16; unsafe{core::arch::asm!("fnstsw {}",out(reg)v)};v }
#[unsafe(no_mangle)] pub unsafe extern "C" fn feclearexcept(e: c_int) -> c_int { mxcsr_wr(mxcsr_rd()&!(e as u32&0x3F));unsafe{core::arch::asm!("fnclex",options(nostack,nomem))};0 }
#[unsafe(no_mangle)] pub unsafe extern "C" fn fegetenv(ep: *mut fenv_t) -> c_int { if ep.is_null(){return -1} unsafe{(*ep).mxcsr=mxcsr_rd();(*ep).x87_cw=cw_rd();(*ep).x87_sw=sw_rd();}0 }