Fix build on x86

This commit is contained in:
Jeremy Soller
2023-11-08 09:54:27 -07:00
parent aacac7e3e0
commit 82fe14960f
+44 -2
View File
@@ -1,3 +1,14 @@
use crate::{
legacy_transport::LegacyTransport,
reinit,
transport::Error,
utils::VolatileCell,
Device,
};
use std::fs::File;
use pcid_interface::*;
pub fn enable_msix(pcid_handle: &mut PcidServerHandle) -> Result<File, Error> {
panic!("virtio-core: x86 doesn't support enable_msix")
}
@@ -6,5 +17,36 @@ pub fn probe_legacy_port_transport<'a>(
pci_header: &PciHeader,
pcid_handle: &mut PcidServerHandle,
) -> Result<Device<'a>, Error> {
crate::x86_64::probe_legacy_port_transport(pci_header, pcid_handle)
}
if let PciBar::Port(port) = pci_header.get_bar(0) {
unsafe { syscall::iopl(3).expect("virtio: failed to set I/O privilege level") };
log::warn!("virtio: using legacy transport");
static SHIM: VolatileCell<u32> = VolatileCell::new(0);
let transport = LegacyTransport::new(port);
// Setup interrupts.
let all_pci_features = pcid_handle.fetch_all_features()?;
let has_msix = all_pci_features
.iter()
.any(|(feature, _)| feature.is_msix());
// According to the virtio specification, the device REQUIRED to support MSI-X.
assert!(has_msix, "virtio: device does not support MSI-X");
let irq_handle = enable_msix(pcid_handle)?;
let device = Device {
transport,
irq_handle,
isr: &SHIM,
device_space: core::ptr::null_mut(),
};
device.transport.reset();
reinit(&device)?;
Ok(device)
} else {
unreachable!("virtio: legacy transport with non-port IO?")
}
}