Remove Option around IDTs HashMap
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@@ -5,7 +5,7 @@ use core::{
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};
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use alloc::boxed::Box;
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use hashbrown::HashMap;
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use hashbrown::{hash_map::DefaultHashBuilder, HashMap};
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use x86::{
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dtables::{self, DescriptorTablePointer},
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@@ -48,20 +48,15 @@ impl Idt {
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static INIT_BSP_IDT: SyncUnsafeCell<Idt> = SyncUnsafeCell::new(Idt::new());
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// TODO: VecMap?
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pub static IDTS: RwLock<Option<HashMap<LogicalCpuId, &'static mut Idt>>> = RwLock::new(None);
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static IDTS: RwLock<HashMap<LogicalCpuId, &'static mut Idt>> =
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RwLock::new(HashMap::with_hasher(DefaultHashBuilder::new()));
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#[inline]
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pub fn is_reserved(cpu_id: LogicalCpuId, index: u8) -> bool {
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let byte_index = index / 32;
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let bit = index % 32;
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IDTS.read()
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.as_ref()
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.unwrap()
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.get(&cpu_id)
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.unwrap()
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.reservations[usize::from(byte_index)]
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.load(Ordering::Acquire)
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IDTS.read().get(&cpu_id).unwrap().reservations[usize::from(byte_index)].load(Ordering::Acquire)
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& (1 << bit)
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!= 0
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}
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@@ -71,13 +66,8 @@ pub fn set_reserved(cpu_id: LogicalCpuId, index: u8, reserved: bool) {
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let byte_index = index / 32;
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let bit = index % 32;
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IDTS.read()
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.as_ref()
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.unwrap()
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.get(&cpu_id)
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.unwrap()
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.reservations[usize::from(byte_index)]
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.fetch_or(u32::from(reserved) << bit, Ordering::AcqRel);
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IDTS.read().get(&cpu_id).unwrap().reservations[usize::from(byte_index)]
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.fetch_or(u32::from(reserved) << bit, Ordering::AcqRel);
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}
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pub fn available_irqs_iter(cpu_id: LogicalCpuId) -> impl Iterator<Item = u8> + 'static {
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@@ -152,8 +142,7 @@ const fn new_idt_reservations() -> [AtomicU32; 8] {
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/// Initialize the IDT for a processor
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pub unsafe fn init_paging_post_heap(cpu_id: LogicalCpuId) {
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unsafe {
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let mut idts_guard = IDTS.write();
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let idts_btree = idts_guard.get_or_insert_with(HashMap::new);
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let mut idts_btree = IDTS.write();
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if cpu_id == LogicalCpuId::BSP {
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idts_btree.insert(cpu_id, &mut *INIT_BSP_IDT.get());
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