xhcid: fix reset procedure on real hardware

xhcid/src/xhci/mod.rs

@@ -49,7 +49,7 @@ use self::doorbell::Doorbell;
 use self::event::EventRing;
 use self::extended::{CapabilityId, ExtendedCapabilitiesIter, ProtocolSpeed, SupportedProtoCap};
 use self::irq_reactor::{EventDoorbell, IrqReactor, NewPendingTrb, RingId};
-use self::operational::OperationalRegs;
+use self::operational::*;
 use self::port::Port;
 use self::ring::Ring;
 use self::runtime::RuntimeRegs;
@@ -372,23 +372,23 @@ impl Xhci {
         let (max_slots, max_ports) = {
             debug!("Waiting for xHC becoming ready.");
             // Wait until controller is ready
-            while op.usb_sts.readf(1 << 11) {
+            while op.usb_sts.readf(USB_STS_CNR) {
                 trace!("Waiting for the xHC to be ready.");
             }
 
             debug!("Stopping the xHC");
             // Set run/stop to 0
-            op.usb_cmd.writef(1, false);
+            op.usb_cmd.writef(USB_CMD_RS, false);
 
             debug!("Waiting for the xHC to stop.");
             // Wait until controller not running
-            while !op.usb_sts.readf(1) {
+            while !op.usb_sts.readf(USB_STS_HCH) {
                 trace!("Waiting for the xHC to stop.");
             }
 
             debug!("Resetting the xHC.");
-            op.usb_cmd.writef(1 << 1, true);
-            while op.usb_sts.readf(1 << 1) {
+            op.usb_cmd.writef(USB_CMD_HCRST, true);
+            while op.usb_cmd.readf(USB_CMD_HCRST) {
                 trace!("Waiting for the xHC to reset.");
             }
 

xhcid/src/xhci/operational.rs

@@ -76,6 +76,16 @@ pub struct OperationalRegs {
     // The standard has 400-13FFh has a Port Register Set here (likely defined in port.rs).
 }
 
+// Run/stop
+pub const USB_CMD_RS: u32 = 1 << 0;
+/// Host controller reset
+pub const USB_CMD_HCRST: u32 = 1 << 1;
+
+/// Host controller halted
+pub const USB_STS_HCH: u32 = 1 << 0;
+/// Host controller not ready
+pub const USB_STS_CNR: u32 = 1 << 11;
+
 /// The mask to get the CIE bit from the Config register. See [OperationalRegs]
 pub const OP_CONFIG_CIE_BIT: u32 = 1 << 9;