Use core::hint::spin_loop() where possible

src/acpi/madt/arch/x86.rs

@@ -1,8 +1,10 @@
-use core::sync::atomic::{AtomicU8, Ordering};
+use core::{
+    hint,
+    sync::atomic::{AtomicU8, Ordering},
+};
 
 use crate::{
     device::local_apic::the_local_apic,
-    interrupt,
     memory::{allocate_p2frame, Frame, KernelMapper},
     paging::{Page, PageFlags, PhysicalAddress, RmmA, RmmArch, VirtualAddress, PAGE_SIZE},
     start::{kstart_ap, AP_READY, CPU_COUNT},
@@ -127,11 +129,11 @@ pub(super) fn init(madt: Madt) {
                             while unsafe { (*ap_ready.cast::<AtomicU8>()).load(Ordering::SeqCst) }
                                 == 0
                             {
-                                interrupt::pause();
+                                hint::spin_loop();
                             }
                             print!(" Trampoline...");
                             while !AP_READY.load(Ordering::SeqCst) {
-                                interrupt::pause();
+                                hint::spin_loop();
                             }
                             println!(" Ready");
 

src/arch/aarch64/interrupt/mod.rs

@@ -50,13 +50,6 @@ pub unsafe fn halt() {
     }
 }
 
-/// Pause instruction
-/// Safe because it is similar to a NOP, and has no memory effects
-#[inline(always)]
-pub fn pause() {
-    unsafe { asm!("nop") };
-}
-
 #[inline(always)]
 pub unsafe fn init() {
     unsafe {

src/arch/aarch64/start.rs

@@ -1,9 +1,11 @@
-/// This function is where the kernel sets up IRQ handlers
-/// It is increcibly unsafe, and should be minimal in nature
-/// It must create the IDT with the correct entries, those entries are
-/// defined in other files inside of the `arch` module
-use core::slice;
-use core::sync::atomic::{AtomicBool, AtomicU32, AtomicUsize, Ordering};
+//! This function is where the kernel sets up IRQ handlers
+//! It is increcibly unsafe, and should be minimal in nature
+//! It must create the IDT with the correct entries, those entries are
+//! defined in other files inside of the `arch` module
+use core::{
+    slice,
+    sync::atomic::{AtomicBool, AtomicU32, AtomicUsize, Ordering},
+};
 
 use fdt::Fdt;
 

src/arch/riscv64/interrupt/mod.rs

@@ -43,16 +43,6 @@ pub unsafe fn halt() {
     unsafe { asm!("wfi", options(nomem, nostack)) }
 }
 
-/// Pause instruction
-/// Safe because it is similar to a NOP, and has no memory effects
-#[inline(always)]
-pub fn pause() {
-    unsafe {
-        // It's a hint instruction, safe to execute without Zihintpause extension
-        asm!("pause", options(nomem, nostack));
-    }
-}
-
 #[inline(always)]
 pub unsafe fn init() {
     unsafe {

src/arch/x86_shared/interrupt/mod.rs

@@ -42,12 +42,3 @@ pub unsafe fn halt() {
         core::arch::asm!("hlt", options(nomem, nostack));
     }
 }
-
-/// Pause instruction
-/// Safe because it is similar to a NOP, and has no memory effects
-#[inline(always)]
-pub fn pause() {
-    unsafe {
-        core::arch::asm!("pause", options(nomem, nostack));
-    }
-}

src/arch/x86_shared/start.rs

@@ -1,10 +1,10 @@
-/// This function is where the kernel sets up IRQ handlers
-/// It is increcibly unsafe, and should be minimal in nature
-/// It must create the IDT with the correct entries, those entries are
-/// defined in other files inside of the `arch` module
-use core::slice;
+//! This function is where the kernel sets up IRQ handlers
+//! It is increcibly unsafe, and should be minimal in nature
+//! It must create the IDT with the correct entries, those entries are
+//! defined in other files inside of the `arch` module
 use core::{
     cell::SyncUnsafeCell,
+    hint, slice,
     sync::atomic::{AtomicBool, AtomicU32, AtomicUsize, Ordering},
 };
 
@@ -294,7 +294,7 @@ pub unsafe extern "C" fn kstart_ap(args_ptr: *const KernelArgsAp) -> ! {
         };
 
         while !BSP_READY.load(Ordering::SeqCst) {
-            interrupt::pause();
+            hint::spin_loop();
         }
 
         crate::kmain_ap(cpu_id);

src/context/switch.rs

@@ -3,7 +3,7 @@
 ///! handling process states and synchronization.
 use core::{
     cell::{Cell, RefCell},
-    mem,
+    hint, mem,
     ops::Bound,
     sync::atomic::Ordering,
 };
@@ -15,7 +15,7 @@ use syscall::PtraceFlags;
 use crate::{
     context::{arch, contexts, Context},
     cpu_set::LogicalCpuId,
-    cpu_stats, interrupt,
+    cpu_stats,
     percpu::PercpuBlock,
     ptrace, time,
 };
@@ -153,7 +153,7 @@ pub fn switch() -> SwitchResult {
         .compare_exchange_weak(false, true, Ordering::SeqCst, Ordering::Relaxed)
         .is_err()
     {
-        interrupt::pause();
+        hint::spin_loop();
         percpu.maybe_handle_tlb_shootdown();
     }