docs: add Phase G entry to CHANGELOG (Arrow Lake / LG Gram 2025 hardware port)

CHANGELOG.md

@@ -132,6 +132,69 @@ sync with the newest highlights.
   - 2 critical gaps remain open, both requiring hardware-specific work
     that can't be done in a QEMU-only session.
 
+### Phase G — Arrow Lake / LG Gram 2025 hardware port (commits `8cd4f69`, `d24d0e217`, `88555c342`, `c335553`)
+
+The LG Gram 16 (2025) is an Intel Core Ultra 7 255H (Arrow Lake-H)
+notebook. This commit documents the Arrow Lake port work delivered
+across the session, mirroring the Phase A–F structure used for
+prior ACPI fork-sync work.
+
+**Phase G.1 — kernel MSR scheme (`8cd4f69`).** The
+`/scheme/sys/msr/{cpu}/0x{msr_hex}` scheme is the critical
+foundation for all P-state, thermal, and RAPL code on Redox
+bare metal. Without it, every MSR write from userspace was a
+silent no-op. The new scheme provides per-CPU per-MSR storage
+with 1024-bucket hashmap backing, validation, and direct scheme
+dispatch. cpufreqd, redbear-power, and the iommu daemon all
+failed silently on real Arrow Lake hardware before this commit.
+
+**Phase G.2 — cpufreqd HWP support (`d24d0e217`).** cpufreqd now
+detects HWP via MSR 0x770 bit 0, reads the HWP range from MSR
+0x771, and writes MSR 0x774 (`IA32_HWP_REQUEST`) with the
+governor-mapped Desired Performance + EPP hint. Falls back to
+legacy `IA32_PERF_CTL` (MSR 0x199) on non-HWP CPUs.
+Redbear-power gets matching HWP MSR constants and accessors
+(`hwp_enabled`, `hwp_capabilities`, `read_hwp_request`,
+`read_hwp_status`) in commit `88555c342`.
+
+**Phase G.6 — acpid `/scheme/acpi/processor/` route (`c335553`).**
+Added `AcpiContext::cpu_names()` which walks the AML symbol
+cache and returns direct child names of `\_PR` whose serialized
+form is a Processor object. New `HandleKind::Processor` and
+`HandleKind::ProcFile` variants in the scheme enable paths
+like `/scheme/acpi/processor/CPU0/pss` that cpufreqd already
+opens. The full AML-to-text export is a follow-up; for now
+`kread` returns a "data not yet populated" placeholder so
+consumers can detect the path is present and report "no data"
+rather than getting ENOENT.
+
+**What was NOT done (out of scope for this session):**
+
+- **Phase G.3** — S0ix (Modern Standby) in kernel. The kernel
+  has no `hlt_loop` in its idle scheduler — it has a logical
+  idle state but no instruction to enter it. Adding mwait-based
+  C-state support and a kernel-side s0ix entry path is a deep
+  kernel change.
+- **Phase G.4** — full C-state driver. Depends on Phase G.3.
+- **Phase G.5** — S0ix device quiesce (GMA + NPU D3Hot). We don't
+  have GMA/NPU support yet in Redox, so there's no driver to put
+  into D3Hot.
+- **Phase G.7** — redbear-power HWP UI / S0ix indicator. The MSR
+  accessors (Phase G.2) provide the data, but the TUI doesn't
+  yet read them on a timer. Phase G.7 was deferred to a follow-up.
+- **Phase G.8** — LG Gram 2025 DMI quirks. Adding a quirk entry
+  for "LG Electronics / 16Z90TR" is straightforward but is
+  cosmetic until driver-level fixes for the platform ship.
+
+**Versions on the 0.2.4 branch (per AGENTS.md § "In-house crate
+versioning"):**
+
+- `local/sources/base` (acpid, hwd, pcid) → 0.1.0 (upstream-tracking)
+- `local/sources/kernel` → upstream (upstream-tracking)
+- `local/recipes/system/cpufreqd` → 0.2.4 ✓
+- `local/recipes/system/redbear-sessiond` → 0.2.4 ✓
+- `local/recipes/system/redbear-power` → 0.2.4 ✓
+
 ### Git server docs (`README.md`, `local/AGENTS.md`, commit `0c60adc6b`)
 
 - Added a canonical **"Our Git Server"** section to both `README.md` and