Merge branch 'less_unstable_use' into 'master'

Reduce usage of unstable features

See merge request redox-os/kernel!230

src/acpi/hpet.rs

@@ -1,6 +1,6 @@
 use core::{mem, ptr};
 
-use core::intrinsics::{volatile_load, volatile_store};
+use core::ptr::{read_volatile, write_volatile};
 
 use crate::memory::Frame;
 use crate::paging::{KernelMapper, PhysicalAddress, PageFlags};
@@ -82,11 +82,11 @@ impl GenericAddressStructure {
     }
 
     pub unsafe fn read_u64(&self, offset: usize) -> u64{
-        volatile_load((crate::HPET_OFFSET + offset) as *const u64)
+        read_volatile((crate::HPET_OFFSET + offset) as *const u64)
     }
 
     pub unsafe fn write_u64(&mut self, offset: usize, value: u64) {
-        volatile_store((crate::HPET_OFFSET + offset) as *mut u64, value);
+        write_volatile((crate::HPET_OFFSET + offset) as *mut u64, value);
     }
 }
 
@@ -103,10 +103,10 @@ impl GenericAddressStructure {
     }
 
     pub unsafe fn read_u64(&self, offset: usize) -> u64{
-        volatile_load((self.address as usize + offset + crate::PHYS_OFFSET) as *const u64)
+        read_volatile((self.address as usize + offset + crate::PHYS_OFFSET) as *const u64)
     }
 
     pub unsafe fn write_u64(&mut self, offset: usize, value: u64) {
-        volatile_store((self.address as usize + offset + crate::PHYS_OFFSET) as *mut u64, value);
+        write_volatile((self.address as usize + offset + crate::PHYS_OFFSET) as *mut u64, value);
     }
 }

src/acpi/madt.rs

@@ -6,8 +6,7 @@ use crate::paging::{KernelMapper, Page, PageFlags, PhysicalAddress, RmmA, RmmArc
 use super::sdt::Sdt;
 use super::find_sdt;
 
-use core::intrinsics::{atomic_load_seqcst, atomic_store_seqcst};
-use core::sync::atomic::Ordering;
+use core::sync::atomic::{AtomicU8, AtomicU64, Ordering};
 
 use crate::device::local_apic::LOCAL_APIC;
 use crate::interrupt;
@@ -73,7 +72,8 @@ impl Madt {
                 // Write trampoline, make sure TRAMPOLINE page is free for use
                 for i in 0..TRAMPOLINE_DATA.len() {
                     unsafe {
-                        atomic_store_seqcst((TRAMPOLINE as *mut u8).add(i), TRAMPOLINE_DATA[i]);
+                        (*((TRAMPOLINE as *mut u8).add(i) as *const AtomicU8))
+                            .store(TRAMPOLINE_DATA[i], Ordering::SeqCst);
                     }
                 }
 
@@ -91,7 +91,7 @@ impl Madt {
                                 let stack_start = allocate_frames(64).expect("no more frames in acpi stack_start").start_address().data() + crate::PHYS_OFFSET;
                                 let stack_end = stack_start + 64 * 4096;
 
-                                let ap_ready = (TRAMPOLINE + 8) as *mut u64;
+                                let ap_ready = (TRAMPOLINE + 8) as *const AtomicU64;
                                 let ap_cpu_id = unsafe { ap_ready.offset(1) };
                                 let ap_page_table = unsafe { ap_ready.offset(2) };
                                 let ap_stack_start = unsafe { ap_ready.offset(3) };
@@ -99,12 +99,17 @@ impl Madt {
                                 let ap_code = unsafe { ap_ready.offset(5) };
 
                                 // Set the ap_ready to 0, volatile
-                                unsafe { atomic_store_seqcst(ap_ready, 0) };
-                                unsafe { atomic_store_seqcst(ap_cpu_id, ap_local_apic.id as u64) };
-                                unsafe { atomic_store_seqcst(ap_page_table, page_table_physaddr as u64) };
-                                unsafe { atomic_store_seqcst(ap_stack_start, stack_start as u64) };
-                                unsafe { atomic_store_seqcst(ap_stack_end, stack_end as u64) };
-                                unsafe { atomic_store_seqcst(ap_code, kstart_ap as u64) };
+                                unsafe {
+                                    (*ap_ready).store(0, Ordering::SeqCst);
+                                    (*ap_cpu_id)
+                                        .store(ap_local_apic.id as u64, Ordering::SeqCst);
+                                    (*ap_page_table)
+                                        .store(page_table_physaddr as u64, Ordering::SeqCst);
+                                    (*ap_stack_start)
+                                        .store(stack_start as u64, Ordering::SeqCst);
+                                    (*ap_stack_end).store(stack_end as u64, Ordering::SeqCst);
+                                    (*ap_code).store(kstart_ap as u64, Ordering::SeqCst);
+                                };
                                 AP_READY.store(false, Ordering::SeqCst);
 
                                 print!("        AP {}:", ap_local_apic.id);
@@ -139,7 +144,7 @@ impl Madt {
 
                                 // Wait for trampoline ready
                                 print!(" Wait...");
-                                while unsafe { atomic_load_seqcst(ap_ready) } == 0 {
+                                while unsafe { (*ap_ready).load(Ordering::SeqCst) } == 0 {
                                     interrupt::pause();
                                 }
                                 print!(" Trampoline...");

src/arch/aarch64/device/gic.rs

@@ -1,4 +1,4 @@
-use core::intrinsics::{volatile_load, volatile_store};
+use core::ptr::{read_volatile, write_volatile};
 
 use crate::memory::Frame;
 use crate::paging::{KernelMapper, PhysicalAddress, Page, PageFlags, TableKind, VirtualAddress};
@@ -149,12 +149,12 @@ impl GicDistIf {
     }
 
     unsafe fn read(&self, reg: u32) -> u32 {
-        let val = volatile_load((self.address + reg as usize) as *const u32);
+        let val = read_volatile((self.address + reg as usize) as *const u32);
         val
     }
 
     unsafe fn write(&mut self, reg: u32, value: u32) {
-        volatile_store((self.address + reg as usize) as *mut u32, value);
+        write_volatile((self.address + reg as usize) as *mut u32, value);
     }
 }
 
@@ -179,11 +179,11 @@ impl GicCpuIf {
     }
 
     unsafe fn read(&self, reg: u32) -> u32 {
-        let val = volatile_load((self.address + reg as usize) as *const u32);
+        let val = read_volatile((self.address + reg as usize) as *const u32);
         val
     }
 
     unsafe fn write(&mut self, reg: u32, value: u32) {
-        volatile_store((self.address + reg as usize) as *mut u32, value);
+        write_volatile((self.address + reg as usize) as *mut u32, value);
     }
 }

src/arch/aarch64/device/rtc.rs

@@ -1,4 +1,4 @@
-use core::intrinsics::{volatile_load, volatile_store};
+use core::ptr::{read_volatile, write_volatile};
 
 use crate::memory::Frame;
 use crate::paging::{KernelMapper, PhysicalAddress, Page, PageFlags, TableKind, VirtualAddress};
@@ -47,12 +47,12 @@ impl Pl031rtc {
     }
 
     unsafe fn read(&self, reg: u32) -> u32 {
-        let val = volatile_load((self.address + reg as usize) as *const u32);
+        let val = read_volatile((self.address + reg as usize) as *const u32);
         val
     }
 
     unsafe fn write(&mut self, reg: u32, value: u32) {
-        volatile_store((self.address + reg as usize) as *mut u32, value);
+        write_volatile((self.address + reg as usize) as *mut u32, value);
     }
 
     pub fn time(&mut self) -> u64 {

src/arch/aarch64/rmm.rs

@@ -57,18 +57,14 @@ pub struct BootloaderMemoryEntry {
 unsafe fn page_flags<A: Arch>(virt: VirtualAddress) -> PageFlags<A> {
     let virt_addr = virt.data();
 
-    // Test for being inside a region
-    macro_rules! in_section {
-        ($n: ident) => {
-            virt_addr >= &concat_idents!(__, $n, _start) as *const u8 as usize
-                && virt_addr < &concat_idents!(__, $n, _end) as *const u8 as usize
-        };
-    }
-
-    if in_section!(text) {
+    if virt_addr >= &__text_start as *const u8 as usize
+        && virt_addr < &__text_end as *const u8 as usize
+    {
         // Remap text read-only, execute
         PageFlags::new().execute(true)
-    } else if in_section!(rodata) {
+    } else if virt_addr >= &__rodata_start as *const u8 as usize
+        && virt_addr < &__rodata_end as *const u8 as usize
+    {
         // Remap rodata read-only, no execute
         PageFlags::new()
     } else {

src/arch/aarch64/stop.rs

@@ -6,9 +6,13 @@ pub unsafe extern fn kreset() -> ! {
 
     let val: u32 = 0x8400_0009;
     asm!("mov   x0, {}", in(reg) val);
-    asm!("hvc   #0");
+    asm!("hvc   #0", options(noreturn));
+}
 
-    unreachable!();
+pub unsafe fn emergency_reset() -> ! {
+    let val: u32 = 0x8400_0009;
+    asm!("mov   x0, {}", in(reg) val);
+    asm!("hvc   #0", options(noreturn));
 }
 
 #[no_mangle]
@@ -17,7 +21,5 @@ pub unsafe extern fn kstop() -> ! {
 
     let val: u32 = 0x8400_0008;
     asm!("mov   x0, {}", in(reg) val);
-    asm!("hvc   #0");
-
-    unreachable!();
+    asm!("hvc   #0", options(noreturn));
 }

src/arch/x86/device/local_apic.rs

@@ -1,5 +1,5 @@
 use core::sync::atomic::{self, AtomicU32};
-use core::intrinsics::{volatile_load, volatile_store};
+use core::ptr::{read_volatile, write_volatile};
 use x86::msr::*;
 
 use crate::paging::{KernelMapper, PhysicalAddress, PageFlags, RmmA, RmmArch, VirtualAddress};
@@ -84,11 +84,11 @@ impl LocalApic {
     }
 
     unsafe fn read(&self, reg: u32) -> u32 {
-        volatile_load((self.address + reg as usize) as *const u32)
+        read_volatile((self.address + reg as usize) as *const u32)
     }
 
     unsafe fn write(&mut self, reg: u32, value: u32) {
-        volatile_store((self.address + reg as usize) as *mut u32, value);
+        write_volatile((self.address + reg as usize) as *mut u32, value);
     }
 
     pub fn id(&self) -> u32 {

src/arch/x86/rmm.rs

@@ -58,18 +58,14 @@ pub struct BootloaderMemoryEntry {
 unsafe fn page_flags<A: Arch>(virt: VirtualAddress) -> PageFlags<A> {
     let virt_addr = virt.data();
 
-    // Test for being inside a region
-    macro_rules! in_section {
-        ($n: ident) => {
-            virt_addr >= &concat_idents!(__, $n, _start) as *const u8 as usize
-                && virt_addr < &concat_idents!(__, $n, _end) as *const u8 as usize
-        };
-    }
-
-    if in_section!(text) {
+    if virt_addr >= &__text_start as *const u8 as usize
+        && virt_addr < &__text_end as *const u8 as usize
+    {
         // Remap text read-only, execute
         PageFlags::new().execute(true)
-    } else if in_section!(rodata) {
+    } else if virt_addr >= &__rodata_start as *const u8 as usize
+        && virt_addr < &__rodata_end as *const u8 as usize
+    {
         // Remap rodata read-only, no execute
         PageFlags::new()
     } else {

src/arch/x86/stop.rs

@@ -19,14 +19,16 @@ pub unsafe extern fn kreset() -> ! {
         port.write(0xFE);
     }
 
+    emergency_reset();
+}
+
+pub unsafe fn emergency_reset() -> ! {
     // Use triple fault to guarantee reset
     core::arch::asm!("
         cli
         lidt cs:0
         int $3
-    ");
-
-    unreachable!();
+    ", options(noreturn));
 }
 
 #[cfg(feature = "acpi")]

src/arch/x86_64/device/local_apic.rs

@@ -1,5 +1,5 @@
 use core::sync::atomic::{self, AtomicU64};
-use core::intrinsics::{volatile_load, volatile_store};
+use core::ptr::{read_volatile, write_volatile};
 use x86::msr::*;
 
 use crate::paging::{KernelMapper, PhysicalAddress, PageFlags, RmmA, RmmArch};
@@ -84,11 +84,11 @@ impl LocalApic {
     }
 
     unsafe fn read(&self, reg: u32) -> u32 {
-        volatile_load((self.address + reg as usize) as *const u32)
+        read_volatile((self.address + reg as usize) as *const u32)
     }
 
     unsafe fn write(&mut self, reg: u32, value: u32) {
-        volatile_store((self.address + reg as usize) as *mut u32, value);
+        write_volatile((self.address + reg as usize) as *mut u32, value);
     }
 
     pub fn id(&self) -> u32 {

src/arch/x86_64/stop.rs

@@ -19,14 +19,16 @@ pub unsafe extern fn kreset() -> ! {
         port.write(0xFE);
     }
 
+    emergency_reset();
+}
+
+pub unsafe fn emergency_reset() -> ! {
     // Use triple fault to guarantee reset
     core::arch::asm!("
         cli
         lidt cs:0
         int $3
-    ");
-
-    unreachable!();
+    ", options(noreturn));
 }
 
 #[cfg(feature = "acpi")]

src/context/memory.rs

@@ -158,16 +158,16 @@ impl AddrSpace {
         }
         Ok(())
     }
-    pub fn munmap(mut self: RwLockWriteGuard<'_, Self>, page: Page, page_count: usize) {
+    pub fn munmap(mut this: RwLockWriteGuard<'_, Self>, page: Page, page_count: usize) {
         let mut notify_files = Vec::new();
 
         let requested = Region::new(page.start_address(), page_count * PAGE_SIZE);
         let mut flusher = PageFlushAll::new();
 
-        let conflicting: Vec<Region> = self.grants.conflicts(requested).map(Region::from).collect();
+        let conflicting: Vec<Region> = this.grants.conflicts(requested).map(Region::from).collect();
 
         for conflict in conflicting {
-            let grant = self.grants.take(&conflict).expect("conflicting region didn't exist");
+            let grant = this.grants.take(&conflict).expect("conflicting region didn't exist");
             let intersection = grant.intersect(requested);
             let (before, mut grant, after) = grant.extract(intersection.round()).expect("conflicting region shared no common parts");
 
@@ -178,16 +178,16 @@ impl AddrSpace {
 
             // Keep untouched regions
             if let Some(before) = before {
-                self.grants.insert(before);
+                this.grants.insert(before);
             }
             if let Some(after) = after {
-                self.grants.insert(after);
+                this.grants.insert(after);
             }
 
             // Remove irrelevant region
-            grant.unmap(&mut self.table.utable, &mut flusher);
+            grant.unmap(&mut this.table.utable, &mut flusher);
         }
-        drop(self);
+        drop(this);
 
         for (file_ref, intersection) in notify_files {
             let scheme_id = { file_ref.desc.description.read().scheme };

src/context/switch.rs

@@ -97,7 +97,7 @@ pub unsafe extern "C" fn switch_finish_hook() {
         next_lock.force_write_unlock();
     } else {
         // TODO: unreachable_unchecked()?
-        core::intrinsics::abort();
+        crate::arch::stop::emergency_reset();
     }
     arch::CONTEXT_SWITCH_LOCK.store(false, Ordering::SeqCst);
 }

src/lib.rs

@@ -44,16 +44,11 @@
 
 #![feature(alloc_error_handler)]
 #![feature(allocator_api)]
-#![feature(arbitrary_self_types)]
 #![feature(array_chunks)]
 #![feature(iter_array_chunks)]
 #![feature(asm_const)] // TODO: Relax requirements of most asm invocations
-#![feature(concat_idents)]
-#![feature(core_intrinsics)]
-#![feature(integer_atomics)]
 #![feature(int_roundings)]
 #![feature(naked_functions)]
-#![feature(ptr_internals)]
 #![feature(slice_ptr_get, slice_ptr_len)]
 #![feature(sync_unsafe_cell)]
 #![feature(thread_local)]

src/scheme/proc.rs

@@ -1030,7 +1030,7 @@ impl KernelScheme for ProcScheme {
                     ADDRSPACE_OP_MUNMAP => {
                         let (page, page_count) = crate::syscall::validate_region(next()??, next()??)?;
 
-                        addrspace.write().munmap(page, page_count);
+                        AddrSpace::munmap(addrspace.write(), page, page_count);
                     }
                     ADDRSPACE_OP_MPROTECT => {
                         let (page, page_count) = crate::syscall::validate_region(next()??, next()??)?;

src/scheme/user.rs

@@ -529,7 +529,7 @@ impl<const READ: bool, const WRITE: bool> CaptureGuard<READ, WRITE> {
 
         let (first_page, page_count, _offset) = page_range_containing(self.base, self.len);
 
-        space.write().munmap(first_page, page_count);
+        AddrSpace::munmap(space.write(), first_page, page_count);
 
         result
     }

src/syscall/fs.rs

@@ -3,6 +3,7 @@ use alloc::sync::Arc;
 use spin::RwLock;
 
 use crate::context::file::{FileDescriptor, FileDescription};
+use crate::context::memory::AddrSpace;
 use crate::context;
 use crate::memory::PAGE_SIZE;
 use crate::scheme::{self, FileHandle, OpenResult, current_caller_ctx, KernelScheme, SchemeId};
@@ -394,7 +395,7 @@ pub fn funmap(virtual_address: usize, length: usize) -> Result<usize> {
     let (page, page_count) = crate::syscall::validate_region(virtual_address, length_aligned)?;
 
     let addr_space = Arc::clone(context::current()?.read().addr_space()?);
-    addr_space.write().munmap(page, page_count);
+    AddrSpace::munmap(addr_space.write(), page, page_count);
 
     Ok(0)
 }

src/syscall/futex.rs

@@ -5,7 +5,7 @@
 use alloc::collections::VecDeque;
 use alloc::sync::Arc;
 use rmm::Arch;
-use core::intrinsics;
+use core::sync::atomic::{AtomicU32, AtomicU64, Ordering};
 use spin::RwLock;
 
 use crate::context::{self, memory::AddrSpace, Context};
@@ -79,7 +79,7 @@ pub fn futex(addr: usize, op: usize, val: usize, val2: usize, addr2: usize) -> R
 
                     (
                         u64::from(unsafe {
-                            intrinsics::atomic_load_seqcst::<u32>(accessible_addr as *const u32)
+                            (*(accessible_addr as *const AtomicU32)).load(Ordering::SeqCst)
                         }),
                         u64::from(val as u32),
                     )
@@ -89,7 +89,7 @@ pub fn futex(addr: usize, op: usize, val: usize, val2: usize, addr2: usize) -> R
                         return Err(Error::new(EINVAL));
                     }
                     (
-                        unsafe { intrinsics::atomic_load_seqcst::<u64>(addr as *const u64) },
+                        u64::from(unsafe { (*(addr as *const AtomicU64)).load(Ordering::SeqCst) }),
                         val as u64,
                     )
                 };