Merge branch 'pcid_cleanup8' into 'master'
Get rid of PciHeader See merge request redox-os/drivers!177
This commit is contained in:
Jeremy Soller
+88
-31
@@ -4,21 +4,23 @@ use std::sync::{Arc, Mutex};
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use std::thread;
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use log::{debug, info, trace, warn};
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use pci_types::{CommandRegister, PciAddress};
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use pci_types::{
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Bar as TyBar, CommandRegister, EndpointHeader, HeaderType, PciAddress,
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PciHeader as TyPciHeader, PciPciBridgeHeader,
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};
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use redox_log::{OutputBuilder, RedoxLogger};
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use structopt::StructOpt;
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use crate::cfg_access::Pcie;
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use crate::config::Config;
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use crate::driver_interface::LegacyInterruptLine;
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use crate::pci_header::{PciEndpointHeader, PciHeader, PciHeaderError};
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use crate::pci::{FullDeviceId, PciBar};
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mod cfg_access;
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mod config;
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mod driver_handler;
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mod driver_interface;
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mod pci;
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mod pci_header;
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#[derive(StructOpt)]
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#[structopt(about)]
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@@ -42,9 +44,14 @@ pub struct State {
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pcie: Pcie,
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}
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fn handle_parsed_header(state: Arc<State>, config: &Config, header: PciEndpointHeader) {
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fn handle_parsed_header(
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state: Arc<State>,
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config: &Config,
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mut endpoint_header: EndpointHeader,
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full_device_id: FullDeviceId,
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) {
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for driver in config.drivers.iter() {
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if !driver.match_function(header.full_device_id()) {
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if !driver.match_function(&full_device_id) {
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continue;
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}
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@@ -52,8 +59,43 @@ fn handle_parsed_header(state: Arc<State>, config: &Config, header: PciEndpointH
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continue;
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};
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let mut bars = [PciBar::None; 6];
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let mut skip = false;
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for i in 0..6 {
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if skip {
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skip = false;
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continue;
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}
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match endpoint_header.bar(i, &state.pcie) {
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Some(TyBar::Io { port }) => {
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bars[i as usize] = PciBar::Port(port.try_into().unwrap())
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}
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Some(TyBar::Memory32 {
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address,
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size,
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prefetchable: _,
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}) => {
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bars[i as usize] = PciBar::Memory32 {
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addr: address,
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size,
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}
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}
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Some(TyBar::Memory64 {
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address,
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size,
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prefetchable: _,
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}) => {
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bars[i as usize] = PciBar::Memory64 {
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addr: address,
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size,
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};
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skip = true; // Each 64bit memory BAR occupies two slots
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}
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None => bars[i as usize] = PciBar::None,
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}
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}
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let mut string = String::new();
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let bars = header.bars(&state.pcie);
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for (i, bar) in bars.iter().enumerate() {
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if !bar.is_none() {
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string.push_str(&format!(" {i}={}", bar.display()));
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@@ -64,8 +106,6 @@ fn handle_parsed_header(state: Arc<State>, config: &Config, header: PciEndpointH
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info!(" BAR{}", string);
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}
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let mut endpoint_header = header.endpoint_header(&state.pcie);
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// Enable bus mastering, memory space, and I/O space
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endpoint_header.update_command(&state.pcie, |cmd| {
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cmd | CommandRegister::BUS_MASTER_ENABLE
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@@ -114,13 +154,13 @@ fn handle_parsed_header(state: Arc<State>, config: &Config, header: PciEndpointH
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let func = driver_interface::PciFunction {
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bars,
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addr: header.address(),
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addr: endpoint_header.header().address(),
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legacy_interrupt_line: if legacy_interrupt_enabled {
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Some(LegacyInterruptLine(irq))
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} else {
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None
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},
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full_device_id: header.full_device_id().clone(),
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full_device_id: full_device_id.clone(),
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};
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driver_handler::DriverHandler::spawn(Arc::clone(&state), func, capabilities, args);
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@@ -227,29 +267,46 @@ fn main(args: Args) {
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'dev: for dev_num in 0..32 {
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for func_num in 0..8 {
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let func_addr = PciAddress::new(0, bus_num, dev_num, func_num);
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match PciHeader::from_reader(&state.pcie, func_addr) {
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Ok(header) => {
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info!("{}", header.display());
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match header {
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PciHeader::General(endpoint_header) => {
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handle_parsed_header(Arc::clone(&state), &config, endpoint_header);
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}
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PciHeader::PciToPci {
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secondary_bus_num, ..
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} => {
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bus_nums.push(secondary_bus_num);
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}
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}
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let header = TyPciHeader::new(PciAddress::new(0, bus_num, dev_num, func_num));
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let (vendor_id, device_id) = header.id(&state.pcie);
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if vendor_id == 0xffff && device_id == 0xffff {
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if func_num == 0 {
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trace!("PCI {:>02X}:{:>02X}: no dev", bus_num, dev_num);
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continue 'dev;
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}
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Err(PciHeaderError::NoDevice) => {
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if func_addr.function() == 0 {
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trace!("PCI {:>02X}:{:>02X}: no dev", bus_num, dev_num);
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continue 'dev;
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}
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continue;
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}
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let (revision, class, subclass, interface) = header.revision_and_class(&state.pcie);
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let full_device_id = FullDeviceId {
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vendor_id,
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device_id,
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class,
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subclass,
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interface,
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revision,
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};
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info!("PCI {} {}", header.address(), full_device_id.display());
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match header.header_type(&state.pcie) {
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HeaderType::Endpoint => {
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handle_parsed_header(
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Arc::clone(&state),
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&config,
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EndpointHeader::from_header(header, &state.pcie).unwrap(),
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full_device_id,
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);
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}
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Err(PciHeaderError::UnknownHeaderType(id)) => {
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warn!("pcid: unknown header type: {id:?}");
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HeaderType::PciPciBridge => {
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let bridge_header =
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PciPciBridgeHeader::from_header(header, &state.pcie).unwrap();
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bus_nums.push(bridge_header.secondary_bus_number(&state.pcie));
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}
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ty => {
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warn!("pcid: unknown header type: {ty:?}");
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}
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}
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}
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@@ -1,3 +1,4 @@
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use pci_types::device_type::DeviceType;
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use serde::{Deserialize, Serialize};
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/// All identifying information of a PCI function.
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@@ -10,3 +11,38 @@ pub struct FullDeviceId {
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pub interface: u8,
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pub revision: u8,
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}
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impl FullDeviceId {
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pub(crate) fn display(&self) -> String {
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let mut string = format!(
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"{:>04X}:{:>04X} {:>02X}.{:>02X}.{:>02X}.{:>02X} {:?}",
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self.vendor_id,
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self.device_id,
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self.class,
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self.subclass,
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self.interface,
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self.revision,
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self.class,
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);
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let device_type = DeviceType::from((self.class, self.subclass));
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match device_type {
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DeviceType::LegacyVgaCompatible => string.push_str(" VGA CTL"),
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DeviceType::IdeController => string.push_str(" IDE"),
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DeviceType::SataController => match self.interface {
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0 => string.push_str(" SATA VND"),
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1 => string.push_str(" SATA AHCI"),
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_ => (),
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},
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DeviceType::UsbController => match self.interface {
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0x00 => string.push_str(" UHCI"),
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0x10 => string.push_str(" OHCI"),
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0x20 => string.push_str(" EHCI"),
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0x30 => string.push_str(" XHCI"),
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_ => (),
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},
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DeviceType::NvmeController => string.push_str(" NVME"),
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_ => (),
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}
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string
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}
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}
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@@ -1,324 +0,0 @@
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use pci_types::device_type::DeviceType;
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use pci_types::{
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Bar as TyBar, ConfigRegionAccess, EndpointHeader, HeaderType, PciAddress,
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PciHeader as TyPciHeader, PciPciBridgeHeader,
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};
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use crate::pci::{FullDeviceId, PciBar};
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#[derive(Debug, PartialEq)]
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pub enum PciHeaderError {
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NoDevice,
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UnknownHeaderType(HeaderType),
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}
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub struct SharedPciHeader {
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full_device_id: FullDeviceId,
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addr: PciAddress,
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}
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub struct PciEndpointHeader {
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shared: SharedPciHeader,
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subsystem_vendor_id: u16,
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subsystem_id: u16,
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}
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum PciHeader {
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General(PciEndpointHeader),
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PciToPci {
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shared: SharedPciHeader,
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secondary_bus_num: u8,
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},
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}
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impl PciHeader {
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/// Parse the bytes found in the Configuration Space of the PCI device into
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/// a more usable PciHeader.
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pub fn from_reader(
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access: &impl ConfigRegionAccess,
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addr: PciAddress,
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) -> Result<PciHeader, PciHeaderError> {
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let header = TyPciHeader::new(addr);
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let (vendor_id, device_id) = header.id(access);
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if vendor_id == 0xffff && device_id == 0xffff {
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return Err(PciHeaderError::NoDevice);
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}
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let (revision, class, subclass, interface) = header.revision_and_class(access);
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let header_type = header.header_type(access);
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let shared = SharedPciHeader {
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full_device_id: FullDeviceId {
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vendor_id,
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device_id,
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class,
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subclass,
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interface,
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revision,
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},
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addr,
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};
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match header_type {
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HeaderType::Endpoint => {
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let endpoint_header = EndpointHeader::from_header(header, access).unwrap();
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let (subsystem_id, subsystem_vendor_id) = endpoint_header.subsystem(access);
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Ok(PciHeader::General(PciEndpointHeader {
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shared,
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subsystem_vendor_id,
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subsystem_id,
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}))
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}
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HeaderType::PciPciBridge => {
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let bridge_header = PciPciBridgeHeader::from_header(header, access).unwrap();
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let secondary_bus_num = bridge_header.secondary_bus_number(access);
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Ok(PciHeader::PciToPci {
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shared,
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secondary_bus_num,
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})
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}
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ty => Err(PciHeaderError::UnknownHeaderType(ty)),
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}
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}
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/// Return all identifying information of the PCI function.
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pub fn full_device_id(&self) -> &FullDeviceId {
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match self {
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PciHeader::General(PciEndpointHeader {
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shared:
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SharedPciHeader {
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full_device_id: device_id,
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..
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},
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..
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})
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| PciHeader::PciToPci {
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shared:
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SharedPciHeader {
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full_device_id: device_id,
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..
|
||||
},
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..
|
||||
} => device_id,
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}
|
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}
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/// Return the PCI address.
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pub fn address(&self) -> PciAddress {
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match self {
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||||
PciHeader::General(header) => header.address(),
|
||||
PciHeader::PciToPci { shared, .. } => shared.addr,
|
||||
}
|
||||
}
|
||||
|
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/// Return the Vendor ID field.
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||||
pub fn vendor_id(&self) -> u16 {
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self.full_device_id().vendor_id
|
||||
}
|
||||
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/// Return the Device ID field.
|
||||
pub fn device_id(&self) -> u16 {
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self.full_device_id().device_id
|
||||
}
|
||||
|
||||
/// Return the Revision field.
|
||||
pub fn revision(&self) -> u8 {
|
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self.full_device_id().revision
|
||||
}
|
||||
|
||||
/// Return the Interface field.
|
||||
pub fn interface(&self) -> u8 {
|
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self.full_device_id().interface
|
||||
}
|
||||
|
||||
/// Return the Subclass field.
|
||||
pub fn subclass(&self) -> u8 {
|
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self.full_device_id().subclass
|
||||
}
|
||||
|
||||
/// Return the Class field.
|
||||
pub fn class(&self) -> u8 {
|
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self.full_device_id().class
|
||||
}
|
||||
|
||||
/// Format a human readable string indicating the address and type of PCI device.
|
||||
pub fn display(&self) -> String {
|
||||
let mut string = format!(
|
||||
"PCI {} {:>04X}:{:>04X} {:>02X}.{:>02X}.{:>02X}.{:>02X} {:?}",
|
||||
self.address(),
|
||||
self.vendor_id(),
|
||||
self.device_id(),
|
||||
self.class(),
|
||||
self.subclass(),
|
||||
self.interface(),
|
||||
self.revision(),
|
||||
self.class()
|
||||
);
|
||||
let device_type = DeviceType::from((self.class(), self.subclass()));
|
||||
match device_type {
|
||||
DeviceType::LegacyVgaCompatible => string.push_str(" VGA CTL"),
|
||||
DeviceType::IdeController => string.push_str(" IDE"),
|
||||
DeviceType::SataController => match self.interface() {
|
||||
0 => string.push_str(" SATA VND"),
|
||||
1 => string.push_str(" SATA AHCI"),
|
||||
_ => (),
|
||||
},
|
||||
DeviceType::UsbController => match self.interface() {
|
||||
0x00 => string.push_str(" UHCI"),
|
||||
0x10 => string.push_str(" OHCI"),
|
||||
0x20 => string.push_str(" EHCI"),
|
||||
0x30 => string.push_str(" XHCI"),
|
||||
_ => (),
|
||||
},
|
||||
_ => (),
|
||||
}
|
||||
string
|
||||
}
|
||||
}
|
||||
|
||||
impl PciEndpointHeader {
|
||||
pub fn address(&self) -> PciAddress {
|
||||
self.shared.addr
|
||||
}
|
||||
|
||||
pub fn endpoint_header(&self, access: &impl ConfigRegionAccess) -> EndpointHeader {
|
||||
EndpointHeader::from_header(TyPciHeader::new(self.shared.addr), access).unwrap()
|
||||
}
|
||||
|
||||
pub fn full_device_id(&self) -> &FullDeviceId {
|
||||
&self.shared.full_device_id
|
||||
}
|
||||
|
||||
/// Return the Headers BARs.
|
||||
pub fn bars(&self, access: &impl ConfigRegionAccess) -> [PciBar; 6] {
|
||||
let endpoint_header = self.endpoint_header(access);
|
||||
|
||||
let mut bars = [PciBar::None; 6];
|
||||
let mut skip = false;
|
||||
for i in 0..6 {
|
||||
if skip {
|
||||
skip = false;
|
||||
continue;
|
||||
}
|
||||
match endpoint_header.bar(i, access) {
|
||||
Some(TyBar::Io { port }) => {
|
||||
bars[i as usize] = PciBar::Port(port.try_into().unwrap())
|
||||
}
|
||||
Some(TyBar::Memory32 {
|
||||
address,
|
||||
size,
|
||||
prefetchable: _,
|
||||
}) => {
|
||||
bars[i as usize] = PciBar::Memory32 {
|
||||
addr: address,
|
||||
size,
|
||||
}
|
||||
}
|
||||
Some(TyBar::Memory64 {
|
||||
address,
|
||||
size,
|
||||
prefetchable: _,
|
||||
}) => {
|
||||
bars[i as usize] = PciBar::Memory64 {
|
||||
addr: address,
|
||||
size,
|
||||
};
|
||||
skip = true; // Each 64bit memory BAR occupies two slots
|
||||
}
|
||||
None => bars[i as usize] = PciBar::None,
|
||||
}
|
||||
}
|
||||
bars
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(test)]
|
||||
mod test {
|
||||
use std::convert::TryInto;
|
||||
|
||||
use pci_types::device_type::DeviceType;
|
||||
use pci_types::{ConfigRegionAccess, PciAddress};
|
||||
|
||||
use super::{PciHeader, PciHeaderError};
|
||||
|
||||
struct TestCfgAccess<'a> {
|
||||
addr: PciAddress,
|
||||
bytes: &'a [u8],
|
||||
}
|
||||
|
||||
impl ConfigRegionAccess for TestCfgAccess<'_> {
|
||||
unsafe fn read(&self, addr: PciAddress, offset: u16) -> u32 {
|
||||
assert_eq!(addr, self.addr);
|
||||
let offset = offset as usize;
|
||||
assert!(offset < self.bytes.len());
|
||||
u32::from_le_bytes(self.bytes[offset..offset + 4].try_into().unwrap())
|
||||
}
|
||||
|
||||
unsafe fn write(&self, _addr: PciAddress, _offset: u16, _value: u32) {
|
||||
unreachable!("should not write during tests");
|
||||
}
|
||||
}
|
||||
|
||||
#[rustfmt::skip]
|
||||
const IGB_DEV_BYTES: [u8; 256] = [
|
||||
0x86, 0x80, 0x33, 0x15, 0x07, 0x04, 0x10, 0x00, 0x03, 0x00, 0x00, 0x02, 0x10, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x50, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x01, 0xb0, 0x00, 0x00, 0x00, 0x00, 0x58, 0xf7,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd9, 0x15, 0x33, 0x15,
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x01, 0x00, 0x00,
|
||||
0x01, 0x50, 0x23, 0xc8, 0x08, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x05, 0x70, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x11, 0xa0, 0x04, 0x80, 0x03, 0x00, 0x00, 0x00, 0x03, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
|
||||
0x10, 0x00, 0x02, 0x00, 0xc2, 0x8c, 0x00, 0x10, 0x0f, 0x28, 0x19, 0x00, 0x11, 0x5c, 0x42, 0x00,
|
||||
0x42, 0x00, 0x11, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
];
|
||||
|
||||
#[test]
|
||||
fn tset_parse_igb_dev() {
|
||||
let header = PciHeader::from_reader(
|
||||
&TestCfgAccess {
|
||||
addr: PciAddress::new(0, 2, 4, 0),
|
||||
bytes: &IGB_DEV_BYTES,
|
||||
},
|
||||
PciAddress::new(0, 2, 4, 0),
|
||||
)
|
||||
.unwrap();
|
||||
match header {
|
||||
PciHeader::General { .. } => {}
|
||||
_ => panic!("wrong header type"),
|
||||
}
|
||||
assert_eq!(header.device_id(), 0x1533);
|
||||
assert_eq!(header.vendor_id(), 0x8086);
|
||||
assert_eq!(header.revision(), 3);
|
||||
assert_eq!(header.interface(), 0);
|
||||
assert_eq!(
|
||||
DeviceType::from((header.class(), header.subclass())),
|
||||
DeviceType::EthernetController
|
||||
);
|
||||
assert_eq!(header.subclass(), 0);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_parse_nonexistent() {
|
||||
let bytes = &[0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff];
|
||||
assert_eq!(
|
||||
PciHeader::from_reader(
|
||||
&TestCfgAccess {
|
||||
addr: PciAddress::new(0, 2, 4, 0),
|
||||
bytes,
|
||||
},
|
||||
PciAddress::new(0, 2, 4, 0),
|
||||
),
|
||||
Err(PciHeaderError::NoDevice)
|
||||
);
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user