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Merge branch 'fix_warnings' into 'master'

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Fix a bunch of warnings

See merge request redox-os/drivers!299
This commit is contained in:
Jeremy Soller
2025-11-29 06:45:24 -07:00
parent 0f24975ffb 420fde3c54
commit 2f90aee27a
14 changed files with 50 additions and 70 deletions
Download Patch File Download Diff File Expand all files Collapse all files
input/ps2d/src/controller.rs
+9 -12
View File
@@ -1,10 +1,10 @@
use common::{io::{Io, Pio, ReadOnly, WriteOnly}, timeout::Timeout};
use log::{debug, error, info, trace};
use std::{
fmt, thread,
time::{Duration, Instant},
use common::{
io::{Io, Pio, ReadOnly, WriteOnly},
timeout::Timeout,
};
use log::{debug, error, trace};
use std::fmt;
#[derive(Debug)]
pub enum Error {
@@ -94,7 +94,6 @@ enum MouseCommand {
#[derive(Clone, Copy, Debug)]
#[repr(u8)]
enum MouseCommandData {
SetResolution = 0xE8,
SetSampleRate = 0xF3,
}
@@ -327,8 +326,6 @@ impl Ps2 {
}
pub fn init_mouse(&mut self) -> Result<bool, Error> {
let mut b: u8 = 0;
{
// Enable second device
self.command(Command::EnableSecond)?;
@@ -368,7 +365,7 @@ impl Ps2 {
}
}
b = self.mouse_command(MouseCommand::GetDeviceId)?;
let b = self.mouse_command(MouseCommand::GetDeviceId)?;
let mouse_extra = if b == 0xFA {
self.read()? == 3
} else {
@@ -379,7 +376,7 @@ impl Ps2 {
{
// Set sample rate to maximum
let sample_rate = 200;
b = self.mouse_command_data(MouseCommandData::SetSampleRate, sample_rate)?;
let b = self.mouse_command_data(MouseCommandData::SetSampleRate, sample_rate)?;
if b != 0xFA {
error!(
"ps2d: mouse failed to set sample rate to {}: {:02X}",
@@ -389,7 +386,7 @@ impl Ps2 {
}
{
b = self.mouse_command(MouseCommand::StatusRequest)?;
let b = self.mouse_command(MouseCommand::StatusRequest)?;
if b != 0xFA {
error!("ps2d: mouse failed to request status: {:02X}", b);
} else {
net/alxd/src/device/mod.rs
+3 -13
View File
@@ -663,7 +663,7 @@ impl Alx {
}
/* clear WoL setting/status */
val = self.read(WOL0);
self.read(WOL0);
self.write(WOL0, 0);
/* deflt val of PDLL D3PLLOFF */
@@ -1124,7 +1124,7 @@ impl Alx {
let mut giga: u16 = 0;
let mut err: usize;
err = self.read_phy_reg(MII_BMSR, &mut bmsr);
self.read_phy_reg(MII_BMSR, &mut bmsr);
err = self.read_phy_reg(MII_BMSR, &mut bmsr);
if (err > 0) {
return err;
@@ -1280,7 +1280,7 @@ impl Alx {
self.write(RXQ0, val);
/* DMA */
val = self.read(DMA);
self.read(DMA);
val = FIELDX!(DMA_RORDER_MODE, DMA_RORDER_MODE_OUT)
| DMA_RREQ_PRI_DATA
| FIELDX!(DMA_RREQ_BLEN, max_payload)
@@ -1726,16 +1726,6 @@ impl Alx {
}
unsafe fn open(&mut self) -> usize {
let _err: usize = 0;
macro_rules! goto_out {
() => {{
self.free_all_ring_resources();
self.disable_advanced_intr();
return err;
}};
}
/* allocate all memory resources */
self.init_ring_ptrs();
net/ixgbed/src/ixgbe.rs
+13 -13
View File
@@ -8,7 +8,7 @@ pub const IXGBE_EIMC: u32 = 0x00888;
pub const IXGBE_CTRL: u32 = 0x00000;
pub const IXGBE_CTRL_LNK_RST: u32 = 0x00000008; /* Link Reset. Resets everything. */
pub const IXGBE_CTRL_RST: u32 = 0x04000000; /* Reset (SW) */
pub const IXGBE_CTRL_RST_MASK: u32 = (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST);
pub const IXGBE_CTRL_RST_MASK: u32 = IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST;
pub const IXGBE_EEC: u32 = 0x10010;
pub const IXGBE_EEC_ARD: u32 = 0x00000200; /* EEPROM Auto Read Done */
@@ -19,11 +19,11 @@ pub const IXGBE_RDRXCTL_DMAIDONE: u32 = 0x00000008; /* DMA init cycle
pub const IXGBE_AUTOC: u32 = 0x042A0;
pub const IXGBE_AUTOC_LMS_SHIFT: u32 = 13;
pub const IXGBE_AUTOC_LMS_MASK: u32 = (0x7 << IXGBE_AUTOC_LMS_SHIFT);
pub const IXGBE_AUTOC_LMS_10G_SERIAL: u32 = (0x3 << IXGBE_AUTOC_LMS_SHIFT);
pub const IXGBE_AUTOC_LMS_MASK: u32 = 0x7 << IXGBE_AUTOC_LMS_SHIFT;
pub const IXGBE_AUTOC_LMS_10G_SERIAL: u32 = 0x3 << IXGBE_AUTOC_LMS_SHIFT;
pub const IXGBE_AUTOC_10G_PMA_PMD_MASK: u32 = 0x00000180;
pub const IXGBE_AUTOC_10G_PMA_PMD_SHIFT: u32 = 7;
pub const IXGBE_AUTOC_10G_XAUI: u32 = (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT);
pub const IXGBE_AUTOC_10G_XAUI: u32 = 0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT;
pub const IXGBE_AUTOC_AN_RESTART: u32 = 0x00001000;
pub const IXGBE_GPRC: u32 = 0x04074;
@@ -37,7 +37,7 @@ pub const IXGBE_RXCTRL: u32 = 0x03000;
pub const IXGBE_RXCTRL_RXEN: u32 = 0x00000001; /* Enable Receiver */
pub fn IXGBE_RXPBSIZE(i: u32) -> u32 {
(0x03C00 + (i * 4))
0x03C00 + (i * 4)
}
pub const IXGBE_RXPBSIZE_128KB: u32 = 0x00020000; /* 128KB Packet Buffer */
@@ -115,7 +115,7 @@ pub const IXGBE_HLREG0_TXCRCEN: u32 = 0x00000001; /* bit 0 */
pub const IXGBE_HLREG0_TXPADEN: u32 = 0x00000400; /* bit 10 */
pub fn IXGBE_TXPBSIZE(i: u32) -> u32 {
(0x0CC00 + (i * 4))
0x0CC00 + (i * 4)
} /* 8 of these */
pub const IXGBE_TXPBSIZE_40KB: u32 = 0x0000A000; /* 40KB Packet Buffer */
@@ -124,16 +124,16 @@ pub const IXGBE_RTTDCS: u32 = 0x04900;
pub const IXGBE_RTTDCS_ARBDIS: u32 = 0x00000040; /* DCB arbiter disable */
pub fn IXGBE_TDBAL(i: u32) -> u32 {
(0x06000 + (i * 0x40))
0x06000 + (i * 0x40)
} /* 32 of them (0-31)*/
pub fn IXGBE_TDBAH(i: u32) -> u32 {
(0x06004 + (i * 0x40))
0x06004 + (i * 0x40)
}
pub fn IXGBE_TDLEN(i: u32) -> u32 {
(0x06008 + (i * 0x40))
0x06008 + (i * 0x40)
}
pub fn IXGBE_TXDCTL(i: u32) -> u32 {
(0x06028 + (i * 0x40))
0x06028 + (i * 0x40)
}
pub const IXGBE_DMATXCTL: u32 = 0x04A80;
@@ -150,10 +150,10 @@ pub const IXGBE_RXDCTL_ENABLE: u32 = 0x02000000; /* Ena specific Rx
pub const IXGBE_TXDCTL_ENABLE: u32 = 0x02000000; /* Ena specific Tx Queue */
pub fn IXGBE_TDH(i: u32) -> u32 {
(0x06010 + (i * 0x40))
0x06010 + (i * 0x40)
}
pub fn IXGBE_TDT(i: u32) -> u32 {
(0x06018 + (i * 0x40))
0x06018 + (i * 0x40)
}
pub const IXGBE_FCTRL_MPE: u32 = 0x00000100; /* Multicast Promiscuous Ena*/
@@ -208,7 +208,7 @@ pub const IXGBE_IVAR_ALLOC_VAL: u32 = 0x80; /* Interrupt Allocation
pub const IXGBE_EICR_RTX_QUEUE: u32 = 0x0000FFFF; /* RTx Queue Interrupt */
pub fn IXGBE_IVAR(i: u32) -> u32 {
(0x00900 + (i * 4))
0x00900 + (i * 4)
} /* 24 at 0x900-0x960 */
#[derive(Debug, Copy, Clone)]
pcid/src/main.rs
-1
View File
@@ -1,4 +1,3 @@
#![feature(non_exhaustive_omitted_patterns_lint)]
#![feature(iter_next_chunk)]
#![feature(if_let_guard)]
storage/ahcid/src/ahci/hba.rs
+1 -1
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@@ -1,7 +1,7 @@
use log::{debug, error, info, trace};
use std::mem::size_of;
use std::ops::DerefMut;
use std::time::{Duration, Instant};
use std::time::Duration;
use std::{ptr, u32};
use common::dma::Dma;
storage/bcm2835-sdhcid/src/main.rs
+1 -3
View File
@@ -1,8 +1,6 @@
#![feature(let_chains)]
use std::process;
use driver_block::{Disk, DiskScheme, ExecutorTrait, TrivialExecutor};
use driver_block::{DiskScheme, ExecutorTrait, TrivialExecutor};
use event::{EventFlags, RawEventQueue};
use fdt::Fdt;
storage/bcm2835-sdhcid/src/sd/mod.rs
+7 -10
View File
@@ -38,7 +38,7 @@ pub(crate) unsafe fn wait_msec(mut n: usize) {
#[cfg(target_arch = "x86_64")]
#[inline(always)]
pub(crate) unsafe fn wait_msec(mut n: usize) {
pub(crate) unsafe fn wait_msec(n: usize) {
thread::sleep(Duration::from_millis(n as u64));
}
@@ -381,11 +381,10 @@ impl SdHostCtrl {
}
pub unsafe fn set_clock(&mut self, freq: u32) -> Result<()> {
let mut cnt: i32 = 0;
let regs = self.regs.get_mut().unwrap();
let mut reg_val = regs.status.read() & (SR_CMD_INHIBIT | SR_DAT_INHIBIT);
cnt = 10_0000;
let mut cnt = 10_0000;
while (cnt > 0) && reg_val != 0 {
wait_msec(1);
cnt -= 1;
@@ -436,7 +435,7 @@ impl SdHostCtrl {
s = 7;
}
}
let mut d = 0;
let mut d;
if self.host_spec_ver > HOST_SPEC_V2 {
d = c;
} else {
@@ -454,7 +453,7 @@ impl SdHostCtrl {
h = (d & 0x300) >> 2;
}
d = (((d & 0xff) << 8) | h);
d = ((d & 0xff) << 8) | h;
reg_val = regs.control1.read() & 0xffff_003f;
regs.control1.write(reg_val | d);
wait_msec(10);
@@ -554,9 +553,9 @@ impl SdHostCtrl {
return Ok(reg_val);
} else if code == CMD_SEND_REL_ADDR {
let mut err = reg_val & 0x1fff;
err |= ((reg_val & 0x2000) << 6);
err |= ((reg_val & 0x4000) << 8);
err |= ((reg_val & 0x8000) << 8);
err |= (reg_val & 0x2000) << 6;
err |= (reg_val & 0x4000) << 8;
err |= (reg_val & 0x8000) << 8;
err &= CMD_ERRORS_MASK;
if err != 0 {
@@ -616,7 +615,6 @@ impl SdHostCtrl {
pub unsafe fn sd_readblock(&mut self, lba: u32, buf: &mut [u32], num: u32) -> Result<usize> {
let num = if num < 1 { 1 } else { num };
let mut reg_val: usize = 0;
//println!("sd_readblock lba 0x{:x}, num 0x{:x}", lba, num);
@@ -672,7 +670,6 @@ impl SdHostCtrl {
pub unsafe fn sd_writeblock(&mut self, lba: u32, buf: &[u32], num: u32) -> Result<usize> {
let num = if num < 1 { 1 } else { num };
let mut reg_val: usize = 0;
//println!("sd_writelock lba 0x{:x}, num 0x{:x}", lba, num);
storage/lived/src/main.rs
+1 -1
View File
@@ -15,7 +15,7 @@ use libredox::flag;
use syscall::error::*;
use syscall::PAGE_SIZE;
use anyhow::{anyhow, bail, Context};
use anyhow::{anyhow, Context};
struct LiveDisk {
original: &'static [u8],
storage/usbscsid/src/scsi/cmds.rs
+1 -1
View File
@@ -552,7 +552,7 @@ impl<'a> Iterator for ModePageIter<'a> {
}
}
pub fn mode_page_iter(buffer: &[u8]) -> impl Iterator<Item = AnyModePage> {
pub fn mode_page_iter(buffer: &[u8]) -> impl Iterator<Item = AnyModePage<'_>> {
ModePageIter {
raw: ModePageIterRaw { buffer },
}
storage/usbscsid/src/scsi/mod.rs
+4 -4
View File
@@ -131,8 +131,8 @@ impl Scsi {
protocol: &mut dyn Protocol,
) -> Result<(
&cmds::ModeParamHeader10,
BlkDescSlice,
impl Iterator<Item = cmds::AnyModePage>,
BlkDescSlice<'_>,
impl Iterator<Item = cmds::AnyModePage<'_>>,
)> {
let initial_alloc_len = mem::size_of::<cmds::ModeParamHeader10>() as u16; // covers both mode_data_len and blk_desc_len.
let mode_sense10 = self.cmd_mode_sense10();
@@ -207,7 +207,7 @@ impl Scsi {
)
.unwrap()
}
pub fn res_blkdesc_mode10(&self) -> BlkDescSlice {
pub fn res_blkdesc_mode10(&self) -> BlkDescSlice<'_> {
let header = self.res_mode_param_header10();
let descs_start = mem::size_of::<cmds::ModeParamHeader10>();
if header.longlba() {
@@ -240,7 +240,7 @@ impl Scsi {
}
}
pub fn res_mode_pages10(&self) -> impl Iterator<Item = cmds::AnyModePage> {
pub fn res_mode_pages10(&self) -> impl Iterator<Item = cmds::AnyModePage<'_>> {
let header = self.res_mode_param_header10();
let descs_start = mem::size_of::<cmds::ModeParamHeader10>();
let buffer = &self.data_buffer[descs_start + header.block_desc_len() as usize..];
usb/usbhubd/src/main.rs
+1 -1
View File
@@ -155,7 +155,7 @@ fn main() {
loop {
for port in 1..=ports {
let port_idx: usize = port.checked_sub(1).unwrap().into();
let mut state = states.get_mut(port_idx).unwrap();
let state = states.get_mut(port_idx).unwrap();
let port_sts = if usb_3 {
let mut port_sts = usb::HubPortStatusV3::default();
usb/xhcid/src/driver_interface.rs
+3 -3
View File
@@ -814,7 +814,7 @@ impl XhciEndpHandle {
pub fn transfer_nodata(&mut self) -> result::Result<PortTransferStatus, XhciClientHandleError> {
self.generic_transfer(XhciEndpCtlDirection::NoData, |_| Ok(0), 0)
}
fn transfer_stream(&mut self, total_len: u32) -> TransferStream {
fn transfer_stream(&mut self, total_len: u32) -> TransferStream<'_> {
TransferStream {
bytes_to_transfer: total_len,
bytes_transferred: 0,
@@ -822,12 +822,12 @@ impl XhciEndpHandle {
endp_handle: self,
}
}
pub fn transfer_write_stream(&mut self, total_len: u32) -> TransferWriteStream {
pub fn transfer_write_stream(&mut self, total_len: u32) -> TransferWriteStream<'_> {
TransferWriteStream {
inner: self.transfer_stream(total_len),
}
}
pub fn transfer_read_stream(&mut self, total_len: u32) -> TransferReadStream {
pub fn transfer_read_stream(&mut self, total_len: u32) -> TransferReadStream<'_> {
TransferReadStream {
inner: self.transfer_stream(total_len),
}
usb/xhcid/src/main.rs
-1
View File
@@ -23,7 +23,6 @@
//! - USB32 - [Universal Serial Bus 3.2 Specification Revision 1.1](https://usb.org/document-library/usb-32-revision-11-june-2022)
//!
#![allow(warnings)]
#![feature(generic_const_exprs)]
#[macro_use]
extern crate bitflags;
virtio-core/src/transport.rs
+6 -6
View File
@@ -270,9 +270,9 @@ impl<'a> Mem<'a> {
match *self {
Self::Owned(ref dma) => dma.as_ptr().cast(),
Self::Borrowed(Borrowed {
phys,
phys: _,
virt,
size,
size: _,
_unused,
}) => virt as *const T,
}
@@ -281,9 +281,9 @@ impl<'a> Mem<'a> {
match *self {
Self::Owned(ref mut dma) => dma.as_mut_ptr().cast(),
Self::Borrowed(Borrowed {
phys,
phys: _,
virt,
size,
size: _,
_unused,
}) => virt as *mut T,
}
@@ -502,7 +502,7 @@ pub trait Transport: Sync + Send {
///
/// ## Panics
/// This function panics if the device is running.
fn setup_queue(&self, vector: u16, irq_handle: &File) -> Result<Arc<Queue>, Error>;
fn setup_queue(&self, vector: u16, irq_handle: &File) -> Result<Arc<Queue<'_>>, Error>;
// TODO(andypython): Should this function be unsafe?
fn reinit_queue(&self, queue: Arc<Queue>);
@@ -615,7 +615,7 @@ impl Transport for StandardTransport<'_> {
u32::from(self.common.lock().unwrap().config_generation.get())
}
fn setup_queue(&self, vector: u16, irq_handle: &File) -> Result<Arc<Queue>, Error> {
fn setup_queue(&self, vector: u16, irq_handle: &File) -> Result<Arc<Queue<'_>>, Error> {
let mut common = self.common.lock().unwrap();
let queue_index = self.queue_index.fetch_add(1, Ordering::SeqCst);