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xhci: Perform both port reset and controller reset

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This commit is contained in:
Jeremy Soller
2022-11-28 06:52:20 -07:00
parent 43375cbe9d
commit 2f15288beb
1 changed files with 23 additions and 1 deletions
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xhcid/src/xhci/mod.rs
+23 -1
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@@ -336,6 +336,17 @@ impl Xhci {
}
pub fn init(&mut self, max_slots: u8) -> Result<()> {
// Set run/stop to 0
debug!("Stopping xHC.");
self.op.get_mut().unwrap().usb_cmd.writef(1, false);
// Warm reset
debug!("Reset xHC");
self.op.get_mut().unwrap().usb_cmd.writef(1 << 1, true);
while self.op.get_mut().unwrap().usb_cmd.readf(1 << 1) {
thread::yield_now();
}
// Set enabled slots
debug!("Setting enabled slots to {}.", max_slots);
self.op.get_mut().unwrap().config.write(max_slots as u32);
@@ -382,7 +393,7 @@ impl Xhci {
self.setup_scratchpads()?;
// Set run/stop to 1
info!("Starting xHC.");
debug!("Starting xHC.");
self.op.get_mut().unwrap().usb_cmd.writef(1, true);
// Wait until controller is running
@@ -472,6 +483,17 @@ impl Xhci {
let port_count = { self.ports.lock().unwrap().len() };
for i in 0..port_count {
//TODO: only reset if USB 2.0?
debug!("Port reset");
{
let port = &mut self.ports.lock().unwrap()[i];
port.portsc.writef(port::PortFlags::PORT_PR.bits(), true);
while port.portsc.readf(port::PortFlags::PORT_PR.bits()) {
//while ! port.flags().contains(port::PortFlags::PORT_PRC) {
std::thread::yield_now();
}
}
let (data, state, speed, flags) = {
let port = &self.ports.lock().unwrap()[i];
(port.read(), port.state(), port.speed(), port.flags())