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intel: add missing xelpg/xelpmp/gen8 WA and fix DG2 CCS scoping

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Admin Pupkin
2026-06-03 08:56:10 +03:00
parent 3fa4e9c895
commit 2d6425ce71
2 changed files with 12 additions and 1 deletions
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local/recipes/gpu/redox-drm/source/src/drivers/intel/regs_gt.rs
+1
View File
@@ -241,6 +241,7 @@ pub const GEN11_GLBLINVL: usize = 0xB404;
pub const HIZ_CHICKEN: usize = 0x7018;
pub const COMMON_SLICE_CHICKEN2: usize = 0x7014;
pub const COMMON_SLICE_CHICKEN4: usize = 0x7300;
pub const XEHP_COMMON_SLICE_CHICKEN3: usize = 0x7304;
pub const VF_PREEMPTION: usize = 0x83A4;
pub const DRAW_WATERMARK: usize = 0x26C0;
pub const GEN10_SAMPLER_MODE: usize = 0xB11C;
local/recipes/gpu/redox-drm/source/src/drivers/intel/workarounds.rs
+11 -1
View File
@@ -343,9 +343,12 @@ fn xelpg_gt_workarounds_init(wal: &mut WorkaroundList, _stepping: u8) {
wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB, "Wa_14018575942");
wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB, "Wa_18018781329");
wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE, "Wa_22016670082");
wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN, "Wa_14014830051");
wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE, "Wa_14015795083");
}
fn xelpmp_gt_workarounds_init(wal: &mut WorkaroundList) {
wa_write_or(wal, VDBOX_CGCTL3F1C, MFXPIPE_CLKGATE_DIS, "Wa_16021867713");
wa_write_or(wal, XELPMP_GSC_MOD_CTRL, FORCE_MISS_FTLB, "Wa_14018778641");
wa_write_or(wal, XELPMP_VDBX_MOD_CTRL, FORCE_MISS_FTLB, "Wa_18018781329_xelpmp");
wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE, "Wa_22016670082_xelpmp");
@@ -395,6 +398,10 @@ fn gen8_ctx_workarounds_init(wal: &mut WorkaroundList) {
wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE, "WaEnableHiZRawStallOpt_ctx");
wa_masked_en(wal, CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE, "Wa4x4STCOptimizationDisable_ctx");
wa_masked_field_set(wal, GEN7_GT_MODE, GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4, "WIZ_HASHING_16x4_ctx");
wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE, "WaDisableThreadStallDopClockGating");
wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, DOP_CLOCK_GATING_DISABLE, "WaDisableDopClockGating");
wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3, GEN8_SAMPLER_POWER_BYPASS_DIS, "WaDisableSamplerPowerBypass");
wa_masked_en(wal, HDC_CHICKEN0, HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT, "WaForceContextSaveRestoreNonCoherent");
}
fn gen9_ctx_workarounds_init(wal: &mut WorkaroundList) {
@@ -537,6 +544,8 @@ fn general_render_compute_wa_init(wal: &mut WorkaroundList, gen: IntelGeneration
wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DISABLE_128B_EVICTION_COMMAND_UDW, "Wa_22013037850");
wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE, "Wa_18017747507");
wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE, "Wa_22014226127");
wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, MTL_DISABLE_SAMPLER_SC_OOO, "Wa_14017066071");
wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, DISABLE_PREFETCH_INTO_IC, "Wa_22015279794");
}
if gen == IntelGeneration::Gen12 {
@@ -650,7 +659,7 @@ fn xcs_engine_wa_init(wal: &mut WorkaroundList, gen: IntelGeneration) {
}
fn ccs_engine_wa_init(wal: &mut WorkaroundList, gen: IntelGeneration) {
if gen == IntelGeneration::GenXe2 {
if gen == IntelGeneration::Gen12 {
wa_masked_en(wal, GEN12_RCU_MODE, XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE, "Wa_14019159160");
wa_masked_en(wal, XEHP_CCS_MODE, 0x1, "XEHP_CCS_MODE_1");
}
@@ -707,6 +716,7 @@ fn icl_whitelist_build(wal: &mut WorkaroundList) {
fn gen12_whitelist_build(wal: &mut WorkaroundList) {
gen9_whitelist_build(wal);
wa_add(wal, XEHP_COMMON_SLICE_CHICKEN3, 0, 0, 0, "XEHP_COMMON_SLICE_CHICKEN3");
wa_add(wal, GEN12_COMMON_SLICE_CHICKEN2, 0, 0, 0, "GEN12_COMMON_SLICE_CHICKEN2");
wa_add(wal, GEN12_VF_PREEMPTION, 0, 0, 0, "GEN12_VF_PREEMPTION");
wa_add(wal, GEN12_VFLSKPD, 0, 0, 0, "GEN12_VFLSKPD");