intel: Phase 3 — wire execlist port and PDP registers

- Create ExeclistPort during driver init with context control registers
- Store execlist_port in IntelDriver for submission routing
- Wire PDP0_LDW/UDW register writes in cs_submit before ring batch

local/recipes/gpu/redox-drm/source/src/drivers/intel/mod.rs

@@ -64,6 +64,7 @@ use self::display_power::DisplayPower;
 use self::display_transcoder::{TransDdiMode, Transcoder};
 use self::display_watermark::DisplayWatermark;
 use self::dp_aux::DpAux;
+use self::execlists::ExeclistPort;
 use self::gmbus::GmbusController;
 use self::gt::IntelGtManager;
 use self::gtt::IntelGtt;
@@ -103,6 +104,7 @@ pub struct IntelDriver {
     encoders: Mutex<Vec<Encoder>>,
     gtt: Mutex<IntelGtt>,
     ring: Mutex<IntelRing>,
+    execlist_port: Mutex<ExeclistPort>,
     gmbus: Option<GmbusController>,
     combo_phy: Option<ComboPhy>,
     display_power: DisplayPower,
@@ -295,6 +297,9 @@ impl IntelDriver {
             (0, false)
         };
 
+        let mut execlist_port = ExeclistPort::new(mmio_arc.clone(), RENDER_RING_BASE);
+        execlist_port.init()?;
+
         let mut guc = GucFirmware::new(mmio_arc.clone());
         if let Some(guc_key) = device_info.guc_fw_key {
             guc.init_wopcm()?;
@@ -378,6 +383,7 @@ impl IntelDriver {
             encoders: Mutex::new(encoders),
             gtt: Mutex::new(gtt),
             ring: Mutex::new(ring),
+            execlist_port: Mutex::new(execlist_port),
             gmbus,
             combo_phy,
             display_power,