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Rustfmt pcid

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This commit is contained in:
bjorn3
2024-06-15 15:58:16 +02:00
parent cd498c1826
commit 2144eaa62c
4 changed files with 101 additions and 33 deletions
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pcid/src/driver_interface/irq_helpers.rs
+38 -16
View File
@@ -20,29 +20,45 @@ pub fn read_bsp_apic_id() -> io::Result<usize> {
(if bytes_read == 8 {
usize::try_from(u64::from_le_bytes(buffer))
} else if bytes_read == 4 {
usize::try_from(u32::from_le_bytes([buffer[0], buffer[1], buffer[2], buffer[3]]))
usize::try_from(u32::from_le_bytes([
buffer[0], buffer[1], buffer[2], buffer[3],
]))
} else {
panic!("`irq:` scheme responded with {} bytes, expected {}", bytes_read, std::mem::size_of::<usize>());
}).or(Err(io::Error::new(io::ErrorKind::InvalidData, "bad BSP int size")))
panic!(
"`irq:` scheme responded with {} bytes, expected {}",
bytes_read,
std::mem::size_of::<usize>()
);
})
.or(Err(io::Error::new(
io::ErrorKind::InvalidData,
"bad BSP int size",
)))
}
// TODO: Perhaps read the MADT instead?
/// Obtains an interator over all of the visible CPU ids, for use in IRQ allocation and MSI
/// capability structs or MSI-X tables.
pub fn cpu_ids() -> io::Result<impl Iterator<Item = io::Result<usize>> + 'static> {
Ok(fs::read_dir("irq:")?
.filter_map(|entry| -> Option<io::Result<_>> { match entry {
Ok(e) => {
let path = e.path();
let file_name = path.file_name()?.to_str()?;
// the file name should be in the format `cpu-<CPU ID>`
if ! file_name.starts_with("cpu-") {
return None;
Ok(
fs::read_dir("irq:")?.filter_map(|entry| -> Option<io::Result<_>> {
match entry {
Ok(e) => {
let path = e.path();
let file_name = path.file_name()?.to_str()?;
// the file name should be in the format `cpu-<CPU ID>`
if !file_name.starts_with("cpu-") {
return None;
}
u8::from_str_radix(&file_name[4..], 16)
.map(usize::from)
.map(Ok)
.ok()
}
u8::from_str_radix(&file_name[4..], 16).map(usize::from).map(Ok).ok()
Err(e) => Some(Err(e)),
}
Err(e) => Some(Err(e)),
} }))
}),
)
}
/// Allocate multiple interrupt vectors, from the IDT of the specified processor, returning the
@@ -62,9 +78,15 @@ pub fn cpu_ids() -> io::Result<impl Iterator<Item = io::Result<usize>> + 'static
/// individually allocated vectors that might be spread out, even on multiple CPUs. Thus, multiple
/// invocations with alignment 1 and count 1 are totally acceptable, although allocating in bulk
/// minimizes the initialization overhead.
pub fn allocate_aligned_interrupt_vectors(cpu_id: usize, alignment: NonZeroU8, count: u8) -> io::Result<Option<(u8, Vec<File>)>> {
pub fn allocate_aligned_interrupt_vectors(
cpu_id: usize,
alignment: NonZeroU8,
count: u8,
) -> io::Result<Option<(u8, Vec<File>)>> {
let cpu_id = u8::try_from(cpu_id).expect("usize cpu ids not implemented yet");
if count == 0 { return Ok(None) }
if count == 0 {
return Ok(None);
}
let available_irqs = fs::read_dir(format!("irq:cpu-{:02x}", cpu_id))?;
let mut available_irq_numbers = available_irqs.filter_map(|entry| -> Option<io::Result<_>> {
pcid/src/driver_interface/mod.rs
+21 -5
View File
@@ -114,7 +114,11 @@ impl FeatureStatus {
}
}
pub fn is_enabled(&self) -> bool {
if let &Self::Enabled = self { true } else { false }
if let &Self::Enabled = self {
true
} else {
false
}
}
}
@@ -125,10 +129,18 @@ pub enum PciFeature {
}
impl PciFeature {
pub fn is_msi(self) -> bool {
if let Self::Msi = self { true } else { false }
if let Self::Msi = self {
true
} else {
false
}
}
pub fn is_msix(self) -> bool {
if let Self::MsiX = self { true } else { false }
if let Self::MsiX = self {
true
} else {
false
}
}
}
#[derive(Debug, Serialize, Deserialize)]
@@ -263,8 +275,12 @@ pub(crate) fn recv<R: Read, T: DeserializeOwned>(r: &mut R) -> Result<T> {
impl PciFunctionHandle {
pub fn connect_default() -> Result<Self> {
let pcid_to_client_fd = env::var("PCID_TO_CLIENT_FD")?.parse::<RawFd>().map_err(PcidClientHandleError::EnvValidityError)?;
let pcid_from_client_fd = env::var("PCID_FROM_CLIENT_FD")?.parse::<RawFd>().map_err(PcidClientHandleError::EnvValidityError)?;
let pcid_to_client_fd = env::var("PCID_TO_CLIENT_FD")?
.parse::<RawFd>()
.map_err(PcidClientHandleError::EnvValidityError)?;
let pcid_from_client_fd = env::var("PCID_FROM_CLIENT_FD")?
.parse::<RawFd>()
.map_err(PcidClientHandleError::EnvValidityError)?;
let mut pcid_to_client = unsafe { File::from_raw_fd(pcid_to_client_fd) };
let mut pcid_from_client = unsafe { File::from_raw_fd(pcid_from_client_fd) };
pcid/src/pci/cap.rs
+6 -5
View File
@@ -1,6 +1,6 @@
use pci_types::capability::PciCapabilityAddress;
use pci_types::ConfigRegionAccess;
use serde::{Serialize, Deserialize};
use serde::{Deserialize, Serialize};
#[derive(Clone, Debug, Eq, Hash, PartialEq, Serialize, Deserialize)]
pub struct VendorSpecificCapability {
@@ -8,7 +8,10 @@ pub struct VendorSpecificCapability {
}
impl VendorSpecificCapability {
pub(crate) unsafe fn parse(addr: PciCapabilityAddress, access: &dyn ConfigRegionAccess) -> Self {
pub(crate) unsafe fn parse(
addr: PciCapabilityAddress,
access: &dyn ConfigRegionAccess,
) -> Self {
let dword = access.read(addr.address, addr.offset);
let next = (dword >> 8) & 0xFF;
let length = ((dword >> 16) & 0xFF) as u16;
@@ -33,8 +36,6 @@ impl VendorSpecificCapability {
log::warn!("Vendor specific capability is invalid");
Vec::new()
};
VendorSpecificCapability {
data
}
VendorSpecificCapability { data }
}
}
pcid/src/pci/msi.rs
+36 -7
View File
@@ -40,10 +40,16 @@ pub struct MsixInfo {
impl MsixInfo {
pub fn validate(&self, bars: [PciBar; 6]) {
if self.table_bar > 5 {
panic!("MSI-X Table BIR contained a reserved enum value: {}", self.table_bar);
panic!(
"MSI-X Table BIR contained a reserved enum value: {}",
self.table_bar
);
}
if self.pba_bar > 5 {
panic!("MSI-X PBA BIR contained a reserved enum value: {}", self.pba_bar);
panic!(
"MSI-X PBA BIR contained a reserved enum value: {}",
self.pba_bar
);
}
let table_size = self.table_size;
@@ -113,23 +119,46 @@ pub mod x86_64 {
}
// TODO: should the reserved field be preserved?
pub const fn message_address(destination_id: u8, redirect_hint: bool, dest_mode_logical: bool) -> u64 {
pub const fn message_address(
destination_id: u8,
redirect_hint: bool,
dest_mode_logical: bool,
) -> u64 {
0x0000_0000_FEE0_0000u64
| ((destination_id as u64) << 12)
| ((redirect_hint as u64) << 3)
| ((dest_mode_logical as u64) << 2)
}
pub const fn message_data(trigger_mode: TriggerMode, level_trigger_mode: LevelTriggerMode, delivery_mode: DeliveryMode, vector: u8) -> u32 {
pub const fn message_data(
trigger_mode: TriggerMode,
level_trigger_mode: LevelTriggerMode,
delivery_mode: DeliveryMode,
vector: u8,
) -> u32 {
((trigger_mode as u32) << 15)
| ((level_trigger_mode as u32) << 14)
| ((delivery_mode as u32) << 8)
| vector as u32
}
pub const fn message_data_level_triggered(level_trigger_mode: LevelTriggerMode, delivery_mode: DeliveryMode, vector: u8) -> u32 {
message_data(TriggerMode::Level, level_trigger_mode, delivery_mode, vector)
pub const fn message_data_level_triggered(
level_trigger_mode: LevelTriggerMode,
delivery_mode: DeliveryMode,
vector: u8,
) -> u32 {
message_data(
TriggerMode::Level,
level_trigger_mode,
delivery_mode,
vector,
)
}
pub const fn message_data_edge_triggered(delivery_mode: DeliveryMode, vector: u8) -> u32 {
message_data(TriggerMode::Edge, LevelTriggerMode::Deassert, delivery_mode, vector)
message_data(
TriggerMode::Edge,
LevelTriggerMode::Deassert,
delivery_mode,
vector,
)
}
}