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Remove PciClass in favor of pci_types::DeviceType

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This commit is contained in:
bjorn3
2024-01-22 16:57:53 +01:00
parent fb0dcb384b
commit 18529f6cee
4 changed files with 25 additions and 117 deletions
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pcid/src/main.rs
+17 -31
View File
@@ -5,6 +5,7 @@ use std::process::Command;
use std::thread;
use std::sync::{Arc, Mutex};
use pci_types::device_type::DeviceType;
use pci_types::{ConfigRegionAccess, PciAddress};
use structopt::StructOpt;
use log::{debug, error, info, warn, trace};
@@ -12,7 +13,7 @@ use redox_log::{OutputBuilder, RedoxLogger};
use crate::cfg_access::Pcie;
use crate::config::Config;
use crate::pci::{PciBar, PciClass, PciFunc};
use crate::pci::{PciBar, PciFunc};
use crate::pci::cap::Capability as PciCapability;
use crate::pci::func::{ConfigReader, ConfigWriter};
use crate::pci_header::{PciHeader, PciHeaderError};
@@ -210,38 +211,23 @@ fn handle_parsed_header(state: Arc<State>, config: &Config, addr: PciAddress, he
let mut string = format!("PCI {} {:>04X}:{:>04X} {:>02X}.{:>02X}.{:>02X}.{:>02X} {:?}",
addr, header.vendor_id(), header.device_id(), raw_class,
header.subclass(), header.interface(), header.revision(), header.class());
match header.class() {
PciClass::Legacy if header.subclass() == 1 => string.push_str(" VGA CTL"),
PciClass::Storage => match header.subclass() {
0x01 => {
string.push_str(" IDE");
},
0x06 => if header.interface() == 0 {
string.push_str(" SATA VND");
} else if header.interface() == 1 {
string.push_str(" SATA AHCI");
},
_ => ()
let device_type = DeviceType::from((header.class(), header.subclass()));
match device_type {
DeviceType::LegacyVgaCompatible => string.push_str(" VGA CTL"),
DeviceType::IdeController => string.push_str(" IDE"),
DeviceType::SataController => match header.interface() {
0 => string.push_str(" SATA VND"),
1 => string.push_str(" SATA AHCI"),
_ => (),
},
PciClass::SerialBus => match header.subclass() {
0x03 => match header.interface() {
0x00 => {
string.push_str(" UHCI");
},
0x10 => {
string.push_str(" OHCI");
},
0x20 => {
string.push_str(" EHCI");
},
0x30 => {
string.push_str(" XHCI");
},
_ => ()
},
_ => ()
DeviceType::UsbController => match header.interface() {
0x00 => string.push_str(" UHCI"),
0x10 => string.push_str(" OHCI"),
0x20 => string.push_str(" EHCI"),
0x30 => string.push_str(" XHCI"),
_ => (),
},
_ => ()
_ => (),
}
let bars = header.bars(&state.pcie);
pcid/src/pci/class.rs
-79
View File
@@ -1,79 +0,0 @@
use serde::{Deserialize, Serialize};
#[derive(Clone, Copy, Debug, PartialEq, Serialize, Deserialize)]
pub enum PciClass {
Legacy,
Storage,
Network,
Display,
Multimedia,
Memory,
Bridge,
SimpleComms,
Peripheral,
Input,
Docking,
Processor,
SerialBus,
Wireless,
IntelligentIo,
SatelliteComms,
Cryptography,
SignalProc,
Reserved(u8),
Unknown
}
impl From<u8> for PciClass {
fn from(class: u8) -> PciClass {
match class {
0x00 => PciClass::Legacy,
0x01 => PciClass::Storage,
0x02 => PciClass::Network,
0x03 => PciClass::Display,
0x04 => PciClass::Multimedia,
0x05 => PciClass::Memory,
0x06 => PciClass::Bridge,
0x07 => PciClass::SimpleComms,
0x08 => PciClass::Peripheral,
0x09 => PciClass::Input,
0x0A => PciClass::Docking,
0x0B => PciClass::Processor,
0x0C => PciClass::SerialBus,
0x0D => PciClass::Wireless,
0x0E => PciClass::IntelligentIo,
0x0F => PciClass::SatelliteComms,
0x10 => PciClass::Cryptography,
0x11 => PciClass::SignalProc,
0xFF => PciClass::Unknown,
reserved => PciClass::Reserved(reserved)
}
}
}
impl Into<u8> for PciClass {
fn into(self) -> u8 {
match self {
PciClass::Legacy => 0x00,
PciClass::Storage => 0x01,
PciClass::Network => 0x02,
PciClass::Display => 0x03,
PciClass::Multimedia => 0x04,
PciClass::Memory => 0x05,
PciClass::Bridge => 0x06,
PciClass::SimpleComms => 0x07,
PciClass::Peripheral => 0x08,
PciClass::Input => 0x09,
PciClass::Docking => 0x0A,
PciClass::Processor => 0x0B,
PciClass::SerialBus => 0x0C,
PciClass::Wireless => 0x0D,
PciClass::IntelligentIo => 0x0E,
PciClass::SatelliteComms => 0x0F,
PciClass::Cryptography => 0x10,
PciClass::SignalProc => 0x11,
PciClass::Unknown => 0xFF,
PciClass::Reserved(reserved) => reserved
}
}
}
pcid/src/pci/mod.rs
-2
View File
@@ -1,12 +1,10 @@
pub use self::bar::PciBar;
pub use self::class::PciClass;
pub use self::func::PciFunc;
pub use self::id::FullDeviceId;
pub use pci_types::PciAddress;
mod bar;
pub mod cap;
mod class;
pub mod func;
mod id;
pub mod msi;
pcid/src/pci_header.rs
+8 -5
View File
@@ -5,7 +5,7 @@ use pci_types::{
PciHeader as TyPciHeader, PciPciBridgeHeader,
};
use crate::pci::{FullDeviceId, PciBar, PciClass};
use crate::pci::{FullDeviceId, PciBar};
#[derive(Debug, PartialEq)]
pub enum PciHeaderError {
@@ -142,8 +142,8 @@ impl PciHeader {
}
/// Return the Class field.
pub fn class(&self) -> PciClass {
PciClass::from(self.full_device_id().class)
pub fn class(&self) -> u8 {
self.full_device_id().class
}
/// Return the Headers BARs.
@@ -221,10 +221,10 @@ impl PciHeader {
mod test {
use std::convert::TryInto;
use pci_types::device_type::DeviceType;
use pci_types::{ConfigRegionAccess, PciAddress};
use super::{PciHeader, PciHeaderError};
use crate::pci::PciClass;
struct TestCfgAccess<'a> {
addr: PciAddress,
@@ -286,7 +286,10 @@ mod test {
assert_eq!(header.vendor_id(), 0x8086);
assert_eq!(header.revision(), 3);
assert_eq!(header.interface(), 0);
assert_eq!(header.class(), PciClass::Network);
assert_eq!(
DeviceType::from((header.class(), header.subclass())),
DeviceType::EthernetController
);
assert_eq!(header.subclass(), 0);
}