enforce two lints and collapse some ifs

Cargo.toml

@@ -49,9 +49,10 @@ module_inception = "allow" # Used for context::context
 # to allocate. If you implement default, it can be allocated without evidence using the
 # ..Default::default() syntax. Not fun in kernel space
 new_without_default = "allow"
-not_unsafe_ptr_arg_deref = "warn" # TODO: address occurrences and then deny
+not_unsafe_ptr_arg_deref = "deny"
 or_fun_call = "allow" # Used to make it nicer to return errors, for example, .ok_or(Error::new(ESRCH))
 precedence = "deny"
+ptr_cast_constness = "deny"
 too_many_arguments = "allow" # This is needed in some cases, like for syscall
 # Avoid panicking in the kernel without information about the panic. Use expect
 # TODO: address occurrences and then deny

src/arch/x86_shared/device/cpu.rs

@@ -229,11 +229,11 @@ pub fn cpu_info<W: Write>(w: &mut W) -> Result {
         };
     }
 
-    if let Some(info) = cpuid.get_advanced_power_mgmt_info() {
-        if info.has_invariant_tsc() {
-            write!(w, " constant_tsc")?
-        };
-    }
+    if let Some(info) = cpuid.get_advanced_power_mgmt_info()
+        && info.has_invariant_tsc()
+    {
+        write!(w, " constant_tsc")?
+    };
 
     if let Some(info) = cpuid.get_extended_feature_info() {
         if info.has_fsgsbase() {

src/arch/x86_shared/device/ioapic.rs

@@ -29,13 +29,13 @@ impl IoApicRegs {
         unsafe { self.pointer.offset(4) }
     }
     fn write_ioregsel(&mut self, value: u32) {
-        unsafe { ptr::write_volatile::<u32>(self.ioregsel() as *mut u32, value) }
+        unsafe { ptr::write_volatile::<u32>(self.ioregsel().cast_mut(), value) }
     }
     fn read_iowin(&self) -> u32 {
         unsafe { ptr::read_volatile::<u32>(self.iowin()) }
     }
     fn write_iowin(&mut self, value: u32) {
-        unsafe { ptr::write_volatile::<u32>(self.iowin() as *mut u32, value) }
+        unsafe { ptr::write_volatile::<u32>(self.iowin().cast_mut(), value) }
     }
     fn read_reg(&mut self, reg: u8) -> u32 {
         self.write_ioregsel(reg.into());

src/context/context.rs

@@ -238,11 +238,11 @@ impl Context {
     pub fn unblock(&mut self) -> bool {
         if self.unblock_no_ipi() {
             // TODO: Only send IPI if currently running?
-            if let Some(cpu_id) = self.cpu_id {
-                if cpu_id != crate::cpu_id() {
-                    // Send IPI if not on current CPU
-                    ipi(IpiKind::Wakeup, IpiTarget::Other);
-                }
+            if let Some(cpu_id) = self.cpu_id
+                && cpu_id != crate::cpu_id()
+            {
+                // Send IPI if not on current CPU
+                ipi(IpiKind::Wakeup, IpiTarget::Other);
             }
 
             true

src/context/switch.rs

@@ -55,13 +55,12 @@ unsafe fn update_runnable(
     }
 
     // If context is soft-blocked and has a wake-up time, check if it should wake up.
-    if context.status.is_soft_blocked() {
-        if let Some(wake) = context.wake {
-            if switch_time >= wake {
-                context.wake = None;
-                context.unblock_no_ipi();
-            }
-        }
+    if context.status.is_soft_blocked()
+        && let Some(wake) = context.wake
+        && switch_time >= wake
+    {
+        context.wake = None;
+        context.unblock_no_ipi();
     }
 
     // If the context is runnable, indicate it can be switched to.

src/log.rs

@@ -53,10 +53,8 @@ impl<'a> Writer<'a> {
     }
 
     pub fn write(&mut self, buf: &[u8], preserve: bool) {
-        if preserve {
-            if let Some(ref mut log) = *self.log {
-                log.write(buf);
-            }
+        if preserve && let Some(ref mut log) = *self.log {
+            log.write(buf);
         }
 
         if let Some(display) = &mut *self.display {

src/profiling.rs

@@ -219,7 +219,7 @@ pub unsafe fn init() {
     let profiling = RingBuffer::create();
 
     BUFS[percpu.cpu_id.get() as usize].store(
-        profiling as *const _ as *mut _,
+        (profiling as *const RingBuffer).cast_mut(),
         core::sync::atomic::Ordering::SeqCst,
     );
     unsafe {

src/scheme/pipe.rs

@@ -485,10 +485,8 @@ impl KernelScheme for PipeScheme {
 
             if !pipe.writer_is_alive.load(Ordering::SeqCst) {
                 return Ok(0);
-            } else {
-                if !pipe.read_condition.wait(vec, "PipeRead::read", token) {
-                    return Err(Error::new(EINTR));
-                }
+            } else if !pipe.read_condition.wait(vec, "PipeRead::read", token) {
+                return Err(Error::new(EINTR));
             }
         }
     }

src/scheme/proc.rs

@@ -449,10 +449,10 @@ impl KernelScheme for ProcScheme {
 
                     Ok(context.set_addr_space(Some(new)))
                 })?;
-                if let Some(old_ctx) = old_ctx {
-                    if let Some(addrspace) = Arc::into_inner(old_ctx) {
-                        addrspace.into_drop(token);
-                    }
+                if let Some(old_ctx) = old_ctx
+                    && let Some(addrspace) = Arc::into_inner(old_ctx)
+                {
+                    addrspace.into_drop(token);
                 }
                 let _ = ptrace::send_event(
                     crate::syscall::ptrace_event!(PTRACE_EVENT_ADDRSPACE_SWITCH, 0),

src/scheme/user.rs

@@ -1329,10 +1329,10 @@ impl<const READ: bool, const WRITE: bool> CaptureGuard<READ, WRITE> {
     }
     pub fn release(mut self, token: &mut CleanLockToken) -> Result<()> {
         self.release_inner()?;
-        if let Some(addrsp) = self.addrsp.take() {
-            if let Some(addrsp) = Arc::into_inner(addrsp) {
-                addrsp.into_drop(token);
-            }
+        if let Some(addrsp) = self.addrsp.take()
+            && let Some(addrsp) = Arc::into_inner(addrsp)
+        {
+            addrsp.into_drop(token);
         }
         if let Some(src) = self.head.src.take() {
             src.into_drop(token);

src/startup/memory.rs

@@ -395,10 +395,10 @@ unsafe fn map_memory<A: Arch>(areas: &[MemoryArea], mut bump_allocator: &mut Bum
 
         debug!("Table: {:X}", mapper.table().phys().data());
         for i in 0..A::PAGE_ENTRIES {
-            if let Some(entry) = mapper.table().entry(i) {
-                if entry.present() {
-                    debug!("{}: {:X}", i, entry.data());
-                }
+            if let Some(entry) = mapper.table().entry(i)
+                && entry.present()
+            {
+                debug!("{}: {:X}", i, entry.data());
             }
         }
 

src/syscall/futex.rs

@@ -146,10 +146,10 @@ pub fn futex(
                     context.wake = timeout_opt.map(|TimeSpec { tv_sec, tv_nsec }| {
                         tv_sec as u128 * time::NANOS_PER_SEC + tv_nsec as u128
                     });
-                    if let Some((tctl, pctl, _)) = context.sigcontrol() {
-                        if tctl.currently_pending_unblocked(pctl) != 0 {
-                            return Err(Error::new(EINTR));
-                        }
+                    if let Some((tctl, pctl, _)) = context.sigcontrol()
+                        && tctl.currently_pending_unblocked(pctl) != 0
+                    {
+                        return Err(Error::new(EINTR));
                     }
 
                     context.block("futex");

src/syscall/time.rs

@@ -43,10 +43,10 @@ pub fn nanosleep(
     {
         let mut context = current_context.write(token.token());
 
-        if let Some((tctl, pctl, _)) = context.sigcontrol() {
-            if tctl.currently_pending_unblocked(pctl) != 0 {
-                return Err(Error::new(EINTR));
-            }
+        if let Some((tctl, pctl, _)) = context.sigcontrol()
+            && tctl.currently_pending_unblocked(pctl) != 0
+        {
+            return Err(Error::new(EINTR));
         }
 
         context.wake = Some(end);