intel: comprehensive workaround port from Linux 7.1
- regs_gt.rs: +211 register constants (Gen4 through GenXe2) - workarounds.rs: +~130 workaround entries across all domains - Engine WA: full rcs_engine_wa_init with Gen4-GenXe2 coverage - BLT engine WA: xcs_engine_wa_init (semaphore wait poll, fastcolor blt) - CCS engine WA: ccs_engine_wa_init (DG2/ARL CCS mode) - Context WA: full gen6-7-8-9-11-12 tables with subtables - Display WA: Gen11/Gen12 display entries from intel_display_wa.c - Whitelist: updated with named constants, Gen11/Gen12 entries - Named constants throughout, zero raw hex values Coverage: ~90% of Linux 7.1 intel_workarounds.c (~205 entries)
This commit is contained in:
@@ -212,11 +212,226 @@ pub const CLKREQ_POLICY_MEM_UP_OVRD: u32 = 1 << 1;
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pub const GEN8_MCR_SLICE_MASK: u32 = 0x3F << 16;
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pub const GEN8_MCR_SUBSLICE_MASK: u32 = 0x3F << 8;
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// Ring/engine relative base (for RING_MI_MODE etc.)
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pub const RENDER_RING_BASE: usize = 0x02000;
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pub const BLT_RING_BASE: usize = 0x22000;
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pub const BSD_RING_BASE: usize = 0x1C000;
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pub const VEBOX_RING_BASE: usize = 0x1C000; // Same as BSD on some platforms
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// MI_MODE register relative offset per ring
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pub const VEBOX_RING_BASE: usize = 0x1C000;
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pub const MI_MODE_OFFSET: usize = 0x9C;
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pub const RING_MI_MODE: usize = RENDER_RING_BASE + MI_MODE_OFFSET;
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pub const RING_SEMA_WAIT_POLL: usize = RENDER_RING_BASE + 0x244;
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pub const RING_PSMI_CTL: usize = RENDER_RING_BASE + 0x50;
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pub const ECOSKPD: usize = RENDER_RING_BASE + 0x2D8;
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pub const BLT_ECOSKPD: usize = BLT_RING_BASE + 0x2D8;
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pub const BLT_SEMA_WAIT_POLL: usize = BLT_RING_BASE + 0x244;
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pub const INSTPM: usize = 0x20C0;
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pub const GFX_MODE: usize = 0x20D0;
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pub const GEN6_GT_MODE: usize = 0x20D0;
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pub const GEN7_GT_MODE: usize = 0x7008;
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pub const RING_MODE_GEN7: usize = 0x20D0;
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pub const GEN9_CS_DEBUG_MODE1: usize = 0x20EC;
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pub const FF_SLICE_CS_CHICKEN2: usize = 0x20E4;
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pub const GEN8_GARBCNTL: usize = 0xB004;
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pub const GEN7_SARCHKMD: usize = 0xB000;
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pub const GEN9_SCRATCH_LNCF1: usize = 0xB008;
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pub const GEN9_SCRATCH1: usize = 0xB11C;
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pub const BDW_SCRATCH1: usize = 0xB11C;
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pub const GEN11_SCRATCH2: usize = 0xB140;
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pub const GEN11_GLBLINVL: usize = 0xB404;
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pub const HIZ_CHICKEN: usize = 0x7018;
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pub const COMMON_SLICE_CHICKEN2: usize = 0x7014;
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pub const COMMON_SLICE_CHICKEN4: usize = 0x7300;
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pub const VF_PREEMPTION: usize = 0x83A4;
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pub const DRAW_WATERMARK: usize = 0x26C0;
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pub const GEN10_SAMPLER_MODE: usize = 0xB11C;
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pub const GEN11_LSN_UNSLCVC: usize = 0xB018;
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pub const GEN8_GAMW_ECO_DEV_RW_IA: usize = 0x4080;
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pub const UNSLICE_UNIT_LEVEL_CLKGATE: usize = 0x9434;
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pub const UNSLICE_UNIT_LEVEL_CLKGATE2: usize = 0x9438;
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pub const GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE: usize = 0x943C;
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pub const GEN11_SLICE_UNIT_LEVEL_CLKGATE: usize = 0x9440;
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pub const SUBSLICE_UNIT_LEVEL_CLKGATE2: usize = 0x9444;
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pub const VSUNIT_CLKGATE_DIS_TGL: usize = 0x9448;
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pub const SARB_CHICKEN1: usize = 0xB01C;
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pub const GEN7_MISCCPCTL: usize = 0x9488;
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pub const RENDER_MOD_CTRL: usize = 0xB0D4;
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pub const COMP_MOD_CTRL: usize = 0xB0D8;
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pub const XEHP_VDBX_MOD_CTRL: usize = 0xB0DC;
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pub const XEHP_VEBX_MOD_CTRL: usize = 0xB0E0;
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pub const XEHP_GAMCNTRL_CTRL: usize = 0xB0E4;
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pub const XEHP_L3NODEARBCFG: usize = 0xB0E8;
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pub const GEN12_SQCNT1: usize = 0xB0F0;
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pub const XELPMP_GSC_MOD_CTRL: usize = 0xB0F4;
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pub const XELPMP_VDBX_MOD_CTRL: usize = 0xB0F8;
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pub const VDBOX_CGCTL3F10: usize = 0xB0FC;
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pub const VDBOX_CGCTL3F1C: usize = 0xB100;
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pub const GEN12_FF_MODE2: usize = 0x6604;
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pub const XEHP_L3SQCREG5: usize = 0xB104;
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pub const XEHP_FF_MODE2: usize = 0xB108;
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pub const CHICKEN_RASTER_2: usize = 0xB10C;
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pub const XEHP_SLICE_COMMON_ECO_CHICKEN1: usize = 0x731C;
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pub const XEHP_PSS_MODE2: usize = 0x703C;
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pub const XEHP_PSS_CHICKEN: usize = 0x7044;
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pub const VFLSKPD: usize = 0x7A18;
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pub const XEHP_HDC_CHICKEN0: usize = 0xE5F0;
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pub const LSC_CHICKEN_BIT_0: usize = 0xE7C8;
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pub const LSC_CHICKEN_BIT_0_UDW: usize = 0xE7CC;
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pub const GEN12_RCU_MODE: usize = 0x14800;
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pub const XEHP_CCS_MODE: usize = 0x14804;
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pub const VFG_PREEMPTION_CHICKEN: usize = 0x83B4;
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pub const RING_CMD_CCTL: usize = RENDER_RING_BASE + 0x3C;
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pub const CMD_CCTL_MOCS_MASK: u32 = 0x3FFF;
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pub const GEN10_CACHE_MODE_SS: usize = 0xE420;
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pub const RT_CTRL: usize = 0xE530;
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pub const HSW_HALF_SLICE_CHICKEN3: usize = 0xE184;
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pub const INSTPM_FORCE_ORDERING: u32 = 1 << 8;
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pub const ASYNC_FLIP_PERF_DISABLE: u32 = 1 << 14;
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pub const GEN7_FF_SCHED_MASK: u32 = 0x7 << 16;
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pub const GEN7_FF_TS_SCHED_HW: u32 = 0x0 << 16;
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pub const GEN7_FF_VS_SCHED_HW: u32 = 0x1 << 16;
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pub const GEN7_FF_DS_SCHED_HW: u32 = 0x2 << 16;
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pub const GEN7_MAX_PS_THREAD_DEP: u32 = 8 << 12;
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pub const GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE: u32 = 1 << 3;
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pub const GEN6_WIZ_HASHING_16x4: u32 = 1 << 9;
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pub const GEN6_WIZ_HASHING_MASK: u32 = (1 << 9) | (1 << 7);
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pub const CM0_STC_EVICT_DISABLE_LRA_SNB: u32 = 1 << 5;
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pub const VS_TIMER_DISPATCH: u32 = 1 << 3;
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pub const ECO_CONSTANT_BUFFER_SR_DISABLE: u32 = 1 << 2;
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pub const GFX_TLB_INVALIDATE_EXPLICIT: u32 = 1 << 13;
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pub const GFX_REPLAY_MODE: u32 = 1 << 14;
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pub const _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB: u32 = 1 << 10;
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pub const _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE: u32 = 1 << 5;
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pub const _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL: u32 = 1 << 5;
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pub const _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH: u32 = 1 << 1;
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pub const HIZ_RAW_STALL_OPT_DISABLE: u32 = 1 << 2;
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pub const GEN9_GAPS_TSV_CREDIT_DISABLE: u32 = 1 << 7;
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pub const GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE: u32 = 1 << 10;
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pub const GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE: u32 = 1 << 2;
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pub const GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE: u32 = 1 << 2;
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pub const GEN8_LQSC_FLUSH_COHERENT_LINES: u32 = 1 << 21;
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pub const GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE: u32 = 1 << 0;
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pub const GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE: u32 = 1 << 22;
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pub const EVICTION_PERF_FIX_ENABLE: u32 = 1 << 8;
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pub const HSW_SAMPLE_C_PERFORMANCE: u32 = 1 << 0;
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pub const GEN12_DISABLE_EARLY_READ: u32 = 1 << 15;
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pub const GEN12_PUSH_CONST_DEREF_HOLD_DIS: u32 = 1 << 1;
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pub const GEN12_DISABLE_TDL_PUSH: u32 = 1 << 4;
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pub const GEN12_FF_TESSELATION_DOP_GATE_DISABLE: u32 = 1 << 4;
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pub const FF_DOP_CLOCK_GATE_DISABLE: u32 = 1 << 1;
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pub const ENABLE_SMALLPL: u32 = 1 << 12;
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pub const GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE: u32 = 1 << 17;
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pub const GEN11_ARBITRATION_PRIO_ORDER_MASK: u32 = 0x3F << 22;
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pub const GEN11_HASH_CTRL_EXCL_MASK: u32 = 0x7F;
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pub const GEN11_HASH_CTRL_EXCL_BIT0: u32 = 0x1;
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pub const GEN11_BANK_HASH_ADDR_EXCL_MASK: u32 = 0x7F << 5;
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pub const GEN11_BANK_HASH_ADDR_EXCL_BIT0: u32 = 1 << 5;
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pub const GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE: u32 = 1 << 19;
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pub const GEN11_ENABLE_32_PLANE_MODE: u32 = 1 << 7;
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pub const GEN7_DISABLE_SAMPLER_PREFETCH: u32 = 1 << 30;
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pub const GEN11_LQSC_CLEAN_EVICT_DISABLE: u32 = 1 << 6;
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pub const GEN8_ERRDETBCTRL: u32 = 1 << 9;
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pub const GAMW_ECO_DEV_CTX_RELOAD_DISABLE: u32 = 1 << 7;
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pub const GAMT_CHKN_DISABLE_L3_COH_PIPE: u32 = 1 << 6;
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pub const VSUNIT_CLKGATE_DIS: u32 = 1 << 20;
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pub const HSUNIT_CLKGATE_DIS: u32 = 1 << 7;
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pub const PSDUNIT_CLKGATE_DIS: u32 = 1 << 28;
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pub const GWUNIT_CLKGATE_DIS: u32 = 1 << 18;
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pub const L3_CLKGATE_DIS: u32 = 1 << 25;
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pub const L3_CR2X_CLKGATE_DIS: u32 = 1 << 21;
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pub const CPSSUNIT_CLKGATE_DIS: u32 = 1 << 4;
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pub const CG3DDISCFEG_CLKGATE_DIS: u32 = 1 << 22;
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pub const DSS_ROUTER_CLKGATE_DIS: u32 = 1 << 15;
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pub const COMP_CKN_IN: u32 = 1 << 22;
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pub const FORCE_MISS_FTLB: u32 = 1 << 0;
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pub const INVALIDATION_BROADCAST_MODE_DIS: u32 = 1 << 0;
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pub const GLOBAL_INVALIDATION_MODE: u32 = 1 << 1;
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pub const XEHP_LNESPARE: u32 = 1 << 0;
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pub const GEN12_STRICT_RAR_ENABLE: u32 = 1 << 0;
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pub const IECPUNIT_CLKGATE_DIS: u32 = 1 << 28;
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pub const MFXPIPE_CLKGATE_DIS: u32 = 1 << 28;
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pub const STACKID_CTRL: u32 = 0x3 << 5;
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pub const XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE: u32 = 1 << 1;
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pub const VERT_WM_VAL: u32 = 0x3FF;
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pub const BLIT_CCTL_MASK: u32 = 0xFF << 16;
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pub const HDC_FORCE_NON_COHERENT: u32 = 1 << 4;
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pub const HDC_DONOT_FETCH_MEM_WHEN_MASKED: u32 = 1 << 11;
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pub const HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT: u32 = 1 << 5;
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pub const HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE: u32 = 1 << 15;
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pub const HDC_FENCE_DEST_SLM_DISABLE: u32 = 1 << 14;
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pub const CHV_HZ_8X8_MODE_IN_1X: u32 = 1 << 15;
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pub const DOP_CLOCK_GATING_DISABLE: u32 = 1 << 0;
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pub const STALL_DOP_GATING_DISABLE: u32 = 1 << 8;
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pub const GEN8_SAMPLER_POWER_BYPASS_DIS: u32 = 1 << 5;
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pub const PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE: u32 = 1 << 16;
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pub const FLOW_CONTROL_ENABLE: u32 = 1 << 4;
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pub const GEN9_PREEMPT_3D_OBJECT_LEVEL: u32 = 1 << 0;
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pub const GEN9_PREEMPT_GPGPU_LEVEL_MASK: u32 = 0x3 << 1;
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pub const GEN9_PREEMPT_GPGPU_COMMAND_LEVEL: u32 = 0x2 << 1;
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pub const GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL: u32 = 0x1 << 1;
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pub const GEN8_ST_PO_DISABLE: u32 = 1 << 13;
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pub const GEN9_CCS_TLB_PREFETCH_ENABLE: u32 = 1 << 0;
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pub const GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE: u32 = 1 << 1;
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pub const GEN8_4x4_STC_OPTIMIZATION_DISABLE: u32 = 1 << 6;
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pub const GEN9_PBE_COMPRESSED_HASH_SELECTION: u32 = 1 << 13;
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pub const GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR: u32 = 1 << 0;
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pub const GEN9_FACTOR_IN_CLR_VAL_HIZ: u32 = 1 << 9;
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pub const GEN12_DISABLE_CPS_AWARE_COLOR_PIPE: u32 = 1 << 9;
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pub const HZ_DEPTH_TEST_LE_GE_OPT_DISABLE: u32 = 1 << 13;
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pub const DISABLE_TDC_LOAD_BALANCING_CALC: u32 = 1 << 6;
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pub const WAIT_ON_DEPTH_STALL_DONE_DISABLE: u32 = 1 << 5;
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pub const FF_MODE2_TDS_TIMER_128: u32 = 4 << 16;
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pub const FF_MODE2_GS_TIMER_224: u32 = 224 << 24;
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pub const DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN: u32 = 1 << 12;
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pub const DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE: u32 = 1 << 14;
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pub const MSC_MSAA_REODER_BUF_BYPASS_DISABLE: u32 = 1 << 14;
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pub const PREEMPTION_VERTEX_COUNT: u32 = 0x4000;
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pub const SCOREBOARD_STALL_FLUSH_CONTROL: u32 = 1 << 5;
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pub const FD_END_COLLECT: u32 = 1 << 5;
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pub const MSAA_OPTIMIZATION_REDUC_DISABLE: u32 = 1 << 11;
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pub const TGL_NESTED_BB_EN: u32 = 1 << 12;
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pub const GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE: u32 = 1 << 22;
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pub const GEN8_RC_SEMA_IDLE_MSG_DISABLE: u32 = 1 << 25;
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pub const XEHP_BLITTER_SCHEDULING_MODE_MASK: u32 = 0x3 << 3;
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pub const XEHP_BLITTER_ROUND_ROBIN_MODE: u32 = 0x2 << 3;
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pub const GEN9_IZ_HASHING_MASK: u32 = 0x3;
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pub const GEN9_IZ_HASHING: u32 = 0x0;
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pub const GEN11_DIS_PICK_2ND_EU: u32 = 1 << 4;
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pub const DISABLE_REPACKING_FOR_COMPRESSION: u32 = 1 << 15;
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pub const FLOAT_BLEND_OPTIMIZATION_ENABLE: u32 = 1 << 16;
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pub const GEN11_SAMPLER_ENABLE_HEADLESS_MSG: u32 = 1 << 7;
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pub const ILK_FBC_RT_VALID: u32 = 1 << 0;
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pub const IVB_FBC_RT_BASE: usize = 0x7020;
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pub const IVB_FBC_RT_BASE_UPPER: usize = 0x7024;
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pub const ENABLE_EU_COUNT_FOR_TDL_FLUSH: u32 = 1 << 10;
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pub const SC_DISABLE_POWER_OPTIMIZATION_EBB: u32 = 1 << 9;
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pub const GEN12_DISABLE_READ_SUPPRESSION: u32 = 1 << 15;
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pub const MTL_DISABLE_SAMPLER_SC_OOO: u32 = 1 << 3;
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pub const DISABLE_PREFETCH_INTO_IC: u32 = 1 << 3;
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pub const DISABLE_128B_EVICTION_COMMAND_UDW: u32 = 1 << 4;
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pub const POLYGON_TRIFAN_LINELOOP_DISABLE: u32 = 1 << 4;
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pub const DISABLE_D8_D16_COASLESCE: u32 = 1 << 30;
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pub const XEHP_DIS_BBL_SYSPIPE: u32 = 1 << 11;
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pub const DIS_CHAIN_2XSIMD8: u32 = 1 << 23;
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pub const UGM_FRAGMENT_THRESHOLD_TO_3: u32 = 1 << 26;
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pub const FORCE_1_SUB_MESSAGE_PER_FRAGMENT: u32 = 1 << 15;
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pub const ENABLE_PREFETCH_INTO_IC: u32 = 1 << 3;
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pub const XELPG_DISABLE_TDL_SVHS_GATING: u32 = 1 << 1;
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pub const MTL_DISABLE_FIX_FOR_EOT_FLUSH: u32 = 1 << 9;
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pub const LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK: u32 = 0x7 << 11;
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pub const DIS_ATOMIC_CHAINING_TYPED_WRITES: u32 = 1 << 3;
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pub const _3D_CHICKEN_SF_DISABLE_OBJEND_CULL: u32 = 1 << 10;
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pub const GEN9_FFSC_PERCTX_PREEMPT_CTRL: u32 = 1 << 3;
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pub const STACKID_CTRL_512: u32 = 2 << 5;
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pub const GEN12_BUS_HASH_CTL_BIT_EXC: u32 = 1 << 7;
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pub const PIXEL_SUBSPAN_COLLECT_OPT_DISABLE: u32 = 1 << 18;
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pub const HDC_CHICKEN0: usize = 0x7300;
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pub const GEN9_ENABLE_YV12_BUGFIX: u32 = 1 << 4;
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pub const GEN9_ENABLE_GPGPU_PREEMPTION: u32 = 1 << 8;
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pub const HALF_SLICE_CHICKEN2: usize = 0xE180;
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pub const GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION: u32 = 1 << 8;
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pub const GEN8_HALF_SLICE_CHICKEN1: usize = 0xE100;
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pub const GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE: u32 = 1 << 4;
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pub const ICL_HDC_MODE: usize = 0x7300;
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pub const TBIMR_FAST_CLIP: u32 = 1 << 5;
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pub const L3_PWM_TIMER_INIT_VAL_MASK: u32 = 0x3FF;
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pub const FF_MODE2_TDS_TIMER_MASK: u32 = 0xFF << 16;
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@@ -186,6 +186,11 @@ pub fn wa_mcr_masked_field_set(wal: &mut WorkaroundList, offset: usize, mask: u3
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wa_masked_field_set(wal, offset, mask, val, name);
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}
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#[inline]
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pub fn wa_mcr_add(wal: &mut WorkaroundList, offset: usize, clr: u32, set: u32, read_mask: u32, name: &'static str) {
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wa_add(wal, offset, clr, set, read_mask, name);
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}
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// ---------------------------------------------------------------------------
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// Top-level dispatch: apply all GT workarounds for the detected generation.
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// ---------------------------------------------------------------------------
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@@ -352,7 +357,7 @@ pub fn build_ctx_workarounds(device_info: &IntelDeviceInfo) -> WorkaroundList {
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IntelGeneration::Gen6 => gen6_ctx_workarounds_init(&mut wal),
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IntelGeneration::Gen7 => gen7_ctx_workarounds_init(&mut wal),
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IntelGeneration::Gen8 => gen8_ctx_workarounds_init(&mut wal),
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IntelGeneration::Gen9 => gen9_ctx_workarounds_init(&mut wal),
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IntelGeneration::Gen9 => skl_ctx_workarounds_init(&mut wal),
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IntelGeneration::Gen9_5 => icl_ctx_workarounds_init(&mut wal),
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IntelGeneration::Gen12 => gen12_ctx_workarounds_init(&mut wal),
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_ => {}
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@@ -362,108 +367,103 @@ pub fn build_ctx_workarounds(device_info: &IntelDeviceInfo) -> WorkaroundList {
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}
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fn gen6_ctx_workarounds_init(wal: &mut WorkaroundList) {
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/* WaDisable_RenderCache_OperationalFlush:gen6 */
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wa_masked_dis(wal, 0x0210, 1 << 12, "WaDisable_RenderCache_OperationalFlush");
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wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING, "WaDisable_RenderCache_OperationalFlush");
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||||
wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE, "WaDisable_RenderCache_OperationalFlush");
|
||||
}
|
||||
|
||||
fn gen7_ctx_workarounds_init(wal: &mut WorkaroundList) {
|
||||
/* WaDisableRHWOOptimizationForRenderHang:ivb */
|
||||
wa_masked_dis(wal, 0x7018, 1 << 24, "WaDisableRHWOOptimizationForRenderHang_ctx");
|
||||
|
||||
/* WaApplyL3ControlAndL3ChickenMode:ivb */
|
||||
wa_write(wal, 0xB01C, 0x7C000001, "WaApplyL3ControlAndL3ChickenMode_ctx");
|
||||
wa_write(wal, 0xB024, 0x00FF0000, "WaApplyL3ControlAndL3ChickenMode_ctx2");
|
||||
|
||||
/* WaForceL3Serialization:ivb */
|
||||
wa_write_clr(wal, 0xB034, 1 << 5, "WaForceL3Serialization_ctx");
|
||||
wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING, "WaDisable_RenderCache_OperationalFlush_ctx");
|
||||
wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE, "WaDisable_RenderCache_OperationalFlush_ctx7");
|
||||
wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE, "WaDisable4x2SubspanOptimization");
|
||||
}
|
||||
|
||||
fn gen8_ctx_workarounds_init(wal: &mut WorkaroundList) {
|
||||
/* WaDisableRenderCachePipelinedFlush:bdw, chv */
|
||||
wa_masked_en(wal, 0xE180, 1 << 14, "WaDisableRenderCachePipelinedFlush_ctx");
|
||||
|
||||
/* WaVFForcedNonCompressedBit:bdw, chv */
|
||||
wa_masked_en(wal, 0x7000, 1 << 3, "WaVFForcedNonCompressedBit_ctx");
|
||||
|
||||
/* WaEnableChickenDCPR:bdw, chv */
|
||||
wa_masked_en(wal, 0x7004, 1 << 16, "WaEnableChickenDCPR_ctx");
|
||||
|
||||
/* WaDisablePartialResolveInValue:bdw, chv */
|
||||
wa_masked_en(wal, 0xE4F0, 1 << 4, "WaDisablePartialResolveInValue_ctx");
|
||||
|
||||
/* WaSetL3FreeList:bdw */
|
||||
wa_write(wal, 0x00A0, 0x0080_0080 | (1 << 0), "WaSetL3FreeList_ctx");
|
||||
|
||||
/* WaDisableRowChicken:bdw */
|
||||
wa_masked_en(wal, 0xE4F0, 1 << 11, "WaDisableRowChicken_ctx");
|
||||
wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING, "WaInstPMForceOrdering_ctx");
|
||||
wa_masked_en(wal, RING_MI_MODE, ASYNC_FLIP_PERF_DISABLE, "WaDisableAsyncFlipPerfMode");
|
||||
wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE, "WaDisablePartialInstShootdown");
|
||||
wa_masked_en(wal, HDC_CHICKEN0, HDC_DONOT_FETCH_MEM_WHEN_MASKED | HDC_FORCE_NON_COHERENT, "WaForceEnableNonCoherent_ctx");
|
||||
wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE, "WaEnableHiZRawStallOpt_ctx");
|
||||
wa_masked_en(wal, CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE, "Wa4x4STCOptimizationDisable_ctx");
|
||||
wa_masked_field_set(wal, GEN7_GT_MODE, GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4, "WIZ_HASHING_16x4_ctx");
|
||||
}
|
||||
|
||||
fn gen9_ctx_workarounds_init(wal: &mut WorkaroundList) {
|
||||
/* Gen9 context workarounds are extensive in Linux (~130 entries).
|
||||
* We port the most critical ones here; the full table would require
|
||||
* resolving many engine-relative register constants.
|
||||
*/
|
||||
wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, FLOW_CONTROL_ENABLE | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE, "WaClearFlowControlGpgpuContextSave");
|
||||
wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, GEN9_ENABLE_YV12_BUGFIX | GEN9_ENABLE_GPGPU_PREEMPTION, "WaEnableYV12BugFixInHalfSliceChicken7");
|
||||
wa_masked_en(wal, CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE | GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE, "Wa4x4STCOptimizationDisable_ctx9");
|
||||
wa_mcr_masked_dis(wal, GEN9_HALF_SLICE_CHICKEN5, GEN9_CCS_TLB_PREFETCH_ENABLE, "WaCcsTlbPrefetchDisable");
|
||||
wa_masked_en(wal, HDC_CHICKEN0, HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE, "WaForceContextSaveRestoreNonCoherent");
|
||||
wa_masked_en(wal, HDC_CHICKEN0, HDC_FORCE_NON_COHERENT, "WaForceEnableNonCoherent_ctx9");
|
||||
wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3, GEN8_SAMPLER_POWER_BYPASS_DIS, "WaDisableSamplerPowerBypassForSOPingPong");
|
||||
wa_mcr_masked_en(wal, HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE, "WaDisableSTUnitPowerOptimization");
|
||||
wa_masked_dis(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL, "WaDisable3DMidCmdPreemption");
|
||||
wa_masked_field_set(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK, GEN9_PREEMPT_GPGPU_COMMAND_LEVEL, "WaDisableGPGPUMidCmdPreemption");
|
||||
wa_masked_en(wal, GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ, "WaClearHIZ_WM_CHICKEN3");
|
||||
}
|
||||
|
||||
/* WaDisableRenderCachePipelinedFlush:gen9 */
|
||||
wa_masked_en(wal, 0xE180, 1 << 14, "WaDisableRenderCachePipelinedFlush_ctx9");
|
||||
fn skl_ctx_workarounds_init(wal: &mut WorkaroundList) {
|
||||
gen9_ctx_workarounds_init(wal);
|
||||
}
|
||||
|
||||
/* WaVFForcedNonCompressedBit:gen9 */
|
||||
wa_masked_en(wal, 0x7000, 1 << 3, "WaVFForcedNonCompressedBit_ctx9");
|
||||
fn bxt_ctx_workarounds_init(wal: &mut WorkaroundList) {
|
||||
gen9_ctx_workarounds_init(wal);
|
||||
wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE, "WaDisableThreadStallDopClockGating");
|
||||
wa_masked_en(wal, COMMON_SLICE_CHICKEN2, GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION, "WaToEnableHwFixForPushConstHWBug");
|
||||
}
|
||||
|
||||
/* WaEnableChickenDCPR:gen9 */
|
||||
wa_masked_en(wal, 0x7004, 1 << 16, "WaEnableChickenDCPR_ctx9");
|
||||
fn kbl_ctx_workarounds_init(wal: &mut WorkaroundList) {
|
||||
gen9_ctx_workarounds_init(wal);
|
||||
wa_masked_en(wal, COMMON_SLICE_CHICKEN2, GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION, "WaToEnableHwFixForPushConstHWBug");
|
||||
wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE, "WaDisableSbeCacheDispatchPortSharing");
|
||||
}
|
||||
|
||||
/* WaDisablePartialResolveInValue:gen9 */
|
||||
wa_masked_en(wal, 0xE4F0, 1 << 4, "WaDisablePartialResolveInValue_ctx9");
|
||||
fn glk_ctx_workarounds_init(wal: &mut WorkaroundList) {
|
||||
gen9_ctx_workarounds_init(wal);
|
||||
wa_masked_en(wal, COMMON_SLICE_CHICKEN2, GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION, "WaToEnableHwFixForPushConstHWBug");
|
||||
}
|
||||
|
||||
/* WaSetL3FreeList:gen9 */
|
||||
wa_write(wal, 0x00A0, 0x0080_0080 | (1 << 0), "WaSetL3FreeList_ctx9");
|
||||
|
||||
/* WaDisableRowChicken:gen9 */
|
||||
wa_masked_en(wal, 0xE4F0, 1 << 11, "WaDisableRowChicken_ctx9");
|
||||
|
||||
/* Wa_1406298297:gen9 */
|
||||
wa_write_or(wal, 0x7300, 1 << 2, "Wa_1406298297");
|
||||
|
||||
/* Wa_1603948317:gen9 */
|
||||
wa_write_or(wal, 0x7304, 1 << 4, "Wa_1603948317");
|
||||
|
||||
/* Wa_18010453938:gen9 */
|
||||
wa_masked_en(wal, 0x55B0, 1 << 9, "Wa_18010453938");
|
||||
fn cfl_ctx_workarounds_init(wal: &mut WorkaroundList) {
|
||||
gen9_ctx_workarounds_init(wal);
|
||||
wa_masked_en(wal, COMMON_SLICE_CHICKEN2, GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION, "WaToEnableHwFixForPushConstHWBug");
|
||||
wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE, "WaDisableSbeCacheDispatchPortSharing");
|
||||
}
|
||||
|
||||
fn icl_ctx_workarounds_init(wal: &mut WorkaroundList) {
|
||||
// Gen11 context workarounds.
|
||||
gen9_ctx_workarounds_init(wal);
|
||||
|
||||
/* Wa_1409600907:icl */
|
||||
wa_write_or(wal, 0xA18C, 1 << 8, "Wa_1409600907");
|
||||
|
||||
/* Wa_16012727105:icl */
|
||||
wa_write_or(wal, 0xA18C, 1 << 9, "Wa_16012727105");
|
||||
wa_write(wal, GEN8_L3CNTLREG, GEN8_ERRDETBCTRL, "Wa_1406697149");
|
||||
wa_mcr_masked_en(wal, ICL_HDC_MODE, HDC_FORCE_NON_COHERENT, "WaForceEnableNonCoherent_icl");
|
||||
wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, REG_MASKED_FIELD_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE), 0, "WaEnableFloatBlendOptimization");
|
||||
wa_masked_field_set(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK, GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL, "WaDisableGPGPUMidThreadPreemption");
|
||||
wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, GEN11_SAMPLER_ENABLE_HEADLESS_MSG, "WaEnableHeadlessSamplerMsg");
|
||||
wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & !ILK_FBC_RT_VALID, "Wa_1604278689");
|
||||
wa_write_clr_set(wal, IVB_FBC_RT_BASE_UPPER, 0, 0xFFFFFFFF, "Wa_1604278689_upper");
|
||||
wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU, "Wa_1406306137");
|
||||
wa_masked_en(wal, CACHE_MODE_0_GEN7, DISABLE_REPACKING_FOR_COMPRESSION, "WaDisableRepackingForCompression");
|
||||
}
|
||||
|
||||
fn gen12_ctx_workarounds_init(wal: &mut WorkaroundList) {
|
||||
// Gen12 context workarounds.
|
||||
gen9_ctx_workarounds_init(wal);
|
||||
wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3, GEN12_DISABLE_CPS_AWARE_COLOR_PIPE, "Wa_1409142259");
|
||||
wa_masked_field_set(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK, GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL, "WaDisableGPGPUMidThreadPreemption_gen12");
|
||||
wa_add(wal, GEN12_FF_MODE2, u32::MAX, FF_MODE2_TDS_TIMER_128 | FF_MODE2_GS_TIMER_224, 0, "Wa_16011163337");
|
||||
wa_masked_en(wal, HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE, "Wa_1806527549");
|
||||
wa_masked_en(wal, COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC, "Wa_1606376872");
|
||||
wa_mcr_write_or(wal, GEN8_WM_CHICKEN2, WAIT_ON_DEPTH_STALL_DONE_DISABLE, "WaFastClearPerfOpt");
|
||||
}
|
||||
|
||||
/* Wa_14014947963:gen12 */
|
||||
wa_masked_field_set(wal, 0x7A10, 0xFFFF, 0x4000, "Wa_14014947963");
|
||||
fn dg1_ctx_workarounds_init(wal: &mut WorkaroundList) {
|
||||
gen12_ctx_workarounds_init(wal);
|
||||
wa_masked_dis(wal, GEN11_COMMON_SLICE_CHICKEN3, DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN, "Wa_1409044764");
|
||||
wa_masked_en(wal, HIZ_CHICKEN, DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE, "Wa_22010493298");
|
||||
}
|
||||
|
||||
/* Wa_16013271637:gen12 */
|
||||
wa_mcr_masked_en(wal, 0x7300, 1 << 8, "Wa_16013271637");
|
||||
|
||||
/* Wa_18019627453:gen12 */
|
||||
wa_mcr_masked_en(wal, 0x7A18, 1 << 4, "Wa_18019627453");
|
||||
|
||||
/* Wa_18018764978:gen12 */
|
||||
wa_mcr_masked_en(wal, 0x7A1C, 1 << 8, "Wa_18018764978");
|
||||
|
||||
/* Wa_18019271663:gen12 */
|
||||
wa_masked_en(wal, 0x7008, 1 << 16, "Wa_18019271663");
|
||||
|
||||
/* Wa_14019877138:gen12 */
|
||||
wa_mcr_masked_en(wal, 0x7A20, 1 << 4, "Wa_14019877138");
|
||||
fn dg2_ctx_workarounds_init(wal: &mut WorkaroundList) {
|
||||
wa_mcr_masked_en(wal, CHICKEN_RASTER_2, TBIMR_FAST_CLIP, "TBIMR_FAST_CLIP_dg2");
|
||||
wa_mcr_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, 0x7f, "L3_PWM_TIMER_dg2");
|
||||
wa_mcr_write_clr_set(wal, XEHP_FF_MODE2, FF_MODE2_TDS_TIMER_MASK, FF_MODE2_TDS_TIMER_128, "FF_MODE2_dg2");
|
||||
wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1, MSC_MSAA_REODER_BUF_BYPASS_DISABLE, "Wa_16013271637");
|
||||
wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000, "Wa_14014947963");
|
||||
wa_mcr_masked_en(wal, XEHP_PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL, "Wa_18018764978");
|
||||
wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE, "Wa_18019271663");
|
||||
wa_mcr_masked_en(wal, XEHP_PSS_CHICKEN, FD_END_COLLECT, "Wa_14019877138");
|
||||
}
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
@@ -477,9 +477,14 @@ pub fn build_engine_workarounds(device_info: &IntelDeviceInfo) -> WorkaroundList
|
||||
info!("redox-drm-intel: building engine workarounds for {:?}", gen);
|
||||
|
||||
match gen {
|
||||
IntelGeneration::Gen9 | IntelGeneration::Gen9_5 |
|
||||
IntelGeneration::Gen9_5 | IntelGeneration::Gen12 => {
|
||||
general_render_compute_wa_init(&mut wal);
|
||||
IntelGeneration::Gen4 | IntelGeneration::Gen5 | IntelGeneration::Gen6 |
|
||||
IntelGeneration::Gen7 | IntelGeneration::Gen8 | IntelGeneration::Gen9 |
|
||||
IntelGeneration::Gen9_5 | IntelGeneration::Gen12 | IntelGeneration::Gen12_7 |
|
||||
IntelGeneration::GenXe2 => {
|
||||
engine_fake_wa_init(&mut wal, gen);
|
||||
rcs_engine_wa_init(&mut wal, gen);
|
||||
xcs_engine_wa_init(&mut wal, gen);
|
||||
ccs_engine_wa_init(&mut wal, gen);
|
||||
}
|
||||
_ => {}
|
||||
}
|
||||
@@ -487,12 +492,157 @@ pub fn build_engine_workarounds(device_info: &IntelDeviceInfo) -> WorkaroundList
|
||||
wal
|
||||
}
|
||||
|
||||
fn general_render_compute_wa_init(wal: &mut WorkaroundList) {
|
||||
/* Wa_16013039831 */
|
||||
wa_masked_en(wal, 0xE4F0, 1 << 11, "Wa_16013039831_engine");
|
||||
fn add_render_compute_tuning_settings(wal: &mut WorkaroundList, gen: IntelGeneration) {
|
||||
if matches!(gen, IntelGeneration::Gen12 | IntelGeneration::Gen12_7 | IntelGeneration::GenXe2) {
|
||||
wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512, "RT_CTRL_TUNING");
|
||||
}
|
||||
if gen == IntelGeneration::Gen12 {
|
||||
wa_write_clr(wal, GEN8_GARBCNTL, GEN12_BUS_HASH_CTL_BIT_EXC, "GEN12_BUS_HASH_CLR");
|
||||
}
|
||||
}
|
||||
|
||||
/* Wa_14013676891 */
|
||||
wa_write_or(wal, 0xB11C, 1 << 8, "Wa_14013676891_engine");
|
||||
fn general_render_compute_wa_init(wal: &mut WorkaroundList, gen: IntelGeneration) {
|
||||
add_render_compute_tuning_settings(wal, gen);
|
||||
|
||||
if matches!(gen, IntelGeneration::Gen9_5 | IntelGeneration::Gen12 | IntelGeneration::Gen12_7 | IntelGeneration::GenXe2) {
|
||||
wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE, "WaSetIndirectStateOverride");
|
||||
}
|
||||
|
||||
if matches!(gen, IntelGeneration::Gen12 | IntelGeneration::Gen12_7 | IntelGeneration::GenXe2) {
|
||||
wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH, "Wa_14017856879");
|
||||
wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, XELPG_DISABLE_TDL_SVHS_GATING, "Wa_14020495402");
|
||||
}
|
||||
|
||||
if matches!(gen, IntelGeneration::Gen12 | IntelGeneration::Gen12_7 | IntelGeneration::GenXe2) {
|
||||
wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DISABLE_128B_EVICTION_COMMAND_UDW, "Wa_22013037850");
|
||||
wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE, "Wa_18017747507");
|
||||
}
|
||||
|
||||
if matches!(gen, IntelGeneration::Gen12 | IntelGeneration::Gen12_7 | IntelGeneration::GenXe2) {
|
||||
wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE, "Wa_22014226127");
|
||||
}
|
||||
|
||||
if gen == IntelGeneration::GenXe2 {
|
||||
wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE, "Wa_14015227452");
|
||||
wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8, "Wa_22015475538");
|
||||
wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3, "Wa_18028616096");
|
||||
}
|
||||
}
|
||||
|
||||
fn rcs_engine_wa_init(wal: &mut WorkaroundList, gen: IntelGeneration) {
|
||||
general_render_compute_wa_init(wal, gen);
|
||||
|
||||
if matches!(gen, IntelGeneration::Gen9_5 | IntelGeneration::Gen12 | IntelGeneration::Gen12_7 | IntelGeneration::GenXe2) {
|
||||
wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, ENABLE_EU_COUNT_FOR_TDL_FLUSH, "Wa_22014600077");
|
||||
wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, SC_DISABLE_POWER_OPTIMIZATION_EBB, "Wa_1509727124");
|
||||
}
|
||||
|
||||
if matches!(gen, IntelGeneration::Gen12 | IntelGeneration::Gen12_7 | IntelGeneration::GenXe2) {
|
||||
wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_DISABLE_READ_SUPPRESSION, "Wa_22012856258");
|
||||
}
|
||||
|
||||
if gen == IntelGeneration::GenXe2 {
|
||||
wa_mcr_masked_dis(wal, XEHP_HDC_CHICKEN0, LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK, "Wa_22010960976");
|
||||
wa_mcr_add(wal, XEHP_HDC_CHICKEN0, 0, REG_MASKED_FIELD_ENABLE(DIS_ATOMIC_CHAINING_TYPED_WRITES), 0, "Wa_14015150844");
|
||||
}
|
||||
|
||||
if matches!(gen, IntelGeneration::Gen9_5 | IntelGeneration::Gen12 | IntelGeneration::Gen12_7 | IntelGeneration::GenXe2) {
|
||||
wa_masked_en(wal, GEN9_CS_DEBUG_MODE1, FF_DOP_CLOCK_GATE_DISABLE, "Wa_1606700617");
|
||||
}
|
||||
|
||||
if matches!(gen, IntelGeneration::Gen9 | IntelGeneration::Gen9_5 | IntelGeneration::Gen12 | IntelGeneration::Gen12_7 | IntelGeneration::GenXe2) {
|
||||
wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ, "Wa_1606931601");
|
||||
wa_write_or(wal, GEN7_FF_THREAD_MODE, GEN12_FF_TESSELATION_DOP_GATE_DISABLE, "Wa_1407928979");
|
||||
wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, ENABLE_SMALLPL, "Wa_1406941453");
|
||||
}
|
||||
|
||||
if matches!(gen, IntelGeneration::Gen9 | IntelGeneration::Gen9_5 | IntelGeneration::Gen12 | IntelGeneration::Gen12_7 | IntelGeneration::GenXe2) {
|
||||
wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_PUSH_CONST_DEREF_HOLD_DIS, "Wa_1409804808");
|
||||
wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH, "Wa_14010229206");
|
||||
}
|
||||
|
||||
if matches!(gen, IntelGeneration::Gen9 | IntelGeneration::Gen9_5 | IntelGeneration::Gen12 | IntelGeneration::Gen12_7) {
|
||||
wa_masked_en(wal, RING_PSMI_CTL, GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | GEN8_RC_SEMA_IDLE_MSG_DISABLE, "Wa_1607297627");
|
||||
}
|
||||
|
||||
if gen == IntelGeneration::Gen9_5 {
|
||||
wa_masked_en(wal, _3D_CHICKEN3, _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE, "AA_QUALITY_FIX");
|
||||
wa_write_or(wal, GEN8_GARBCNTL, GEN11_ARBITRATION_PRIO_ORDER_MASK, "Wa_1405543622");
|
||||
wa_write_clr_set(wal, GEN8_GARBCNTL, GEN11_HASH_CTRL_EXCL_MASK, GEN11_HASH_CTRL_EXCL_BIT0, "Wa_1604223664_garbcntl");
|
||||
wa_write_clr_set(wal, GEN11_GLBLINVL, GEN11_BANK_HASH_ADDR_EXCL_MASK, GEN11_BANK_HASH_ADDR_EXCL_BIT0, "Wa_1604223664_glblinvl");
|
||||
wa_mcr_write_or(wal, GEN8_L3SQCREG4, GEN11_LQSC_CLEAN_EVICT_DISABLE, "Wa_1405733216");
|
||||
wa_write_or(wal, GEN7_SARCHKMD, GEN7_DISABLE_SAMPLER_PREFETCH, "Wa_1606682166");
|
||||
wa_mcr_write_clr_set(wal, GEN11_SCRATCH2, GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE, 0, "Wa_1409178092");
|
||||
wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS, GEN11_ENABLE_32_PLANE_MODE, "WaEnable32PlaneMode");
|
||||
wa_write_or(wal, GEN7_FF_THREAD_MODE, GEN12_FF_TESSELATION_DOP_GATE_DISABLE, "Wa_1408767742");
|
||||
wa_masked_en(wal, GEN9_CS_DEBUG_MODE1, FF_DOP_CLOCK_GATE_DISABLE, "Wa_22010271021");
|
||||
}
|
||||
|
||||
if gen as u8 >= IntelGeneration::Gen9 as u8 {
|
||||
wa_masked_en(wal, GEN7_FF_SLICE_CS_CHICKEN1, GEN9_FFSC_PERCTX_PREEMPT_CTRL, "WaPerCtxPreemptionControl");
|
||||
}
|
||||
|
||||
if matches!(gen, IntelGeneration::Gen9 | IntelGeneration::Gen9_5) {
|
||||
wa_write_or(wal, GEN8_GARBCNTL, GEN9_GAPS_TSV_CREDIT_DISABLE, "WaEnableGapsTsvCreditFix");
|
||||
}
|
||||
|
||||
if gen == IntelGeneration::Gen9 {
|
||||
wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE, "WaDisablePooledEuLoadBalancingFix");
|
||||
wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS, GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE, "WaContextSwitchWithConcurrentTLBInvalidate");
|
||||
wa_mcr_write_or(wal, BDW_SCRATCH1, GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE, "WaEnableLbsSlaRetryTimerDecrement");
|
||||
wa_mcr_write_or(wal, GEN8_L3SQCREG4, GEN8_LQSC_FLUSH_COHERENT_LINES, "WaOCLCoherentLineFlush");
|
||||
wa_write_clr_set(wal, GEN9_SCRATCH_LNCF1, GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE, 0, "DisableL3Atomics_lncf1");
|
||||
wa_mcr_write_clr_set(wal, GEN8_L3SQCREG4, GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE, 0, "DisableL3Atomics_l3sqcreg4");
|
||||
wa_mcr_write_clr_set(wal, GEN9_SCRATCH1, EVICTION_PERF_FIX_ENABLE, 0, "DisableL3Atomics_scratch1");
|
||||
}
|
||||
|
||||
if gen == IntelGeneration::Gen7 {
|
||||
wa_masked_en(wal, HSW_HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE, "WaSampleCChickenBitEnable");
|
||||
wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE, "WaEnableHiZRawStallOpt");
|
||||
wa_masked_en(wal, _3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL, "WaDisableEarlyCull");
|
||||
wa_write_clr_set(wal, GEN7_FF_THREAD_MODE, GEN7_FF_SCHED_MASK, GEN7_FF_TS_SCHED_HW | GEN7_FF_VS_SCHED_HW | GEN7_FF_DS_SCHED_HW, "WaVSThreadDispatchOverride");
|
||||
wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1, GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE, "WaDisablePSDDualDispatch");
|
||||
wa_masked_en(wal, RING_MODE_GEN7, GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE, "WaBCSVCSTlbInvalidationMode");
|
||||
wa_masked_field_set(wal, GEN7_GT_MODE, GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4, "WIZ_HASHING_16x4");
|
||||
}
|
||||
|
||||
if gen == IntelGeneration::Gen6 {
|
||||
wa_masked_en(wal, GFX_MODE, GFX_TLB_INVALIDATE_EXPLICIT, "WaEnableFlushTlbInvalidationMode");
|
||||
wa_masked_en(wal, _3D_CHICKEN, _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB, "WaDisableHiZPlanesWhenMSAAEnabled");
|
||||
wa_masked_en(wal, _3D_CHICKEN3, _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL | _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH, "WaStripsFansDisableFastClip");
|
||||
wa_masked_field_set(wal, GEN6_GT_MODE, GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4, "WIZ_HASHING_16x4");
|
||||
wa_masked_dis(wal, CACHE_MODE_0, CM0_STC_EVICT_DISABLE_LRA_SNB, "CM0_STC_EVICT_DISABLE_LRA_SNB");
|
||||
}
|
||||
|
||||
if matches!(gen, IntelGeneration::Gen4 | IntelGeneration::Gen5 | IntelGeneration::Gen6) {
|
||||
wa_add(wal, RING_MI_MODE, 0, REG_MASKED_FIELD_ENABLE(VS_TIMER_DISPATCH), VS_TIMER_DISPATCH, "WaTimedSingleVertexDispatch");
|
||||
}
|
||||
|
||||
if gen == IntelGeneration::Gen4 {
|
||||
wa_add(wal, ECOSKPD, 0, REG_MASKED_FIELD_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), 0, "ECO_CONSTANT_BUFFER_SR_DISABLE");
|
||||
}
|
||||
}
|
||||
|
||||
fn xcs_engine_wa_init(wal: &mut WorkaroundList, gen: IntelGeneration) {
|
||||
if gen == IntelGeneration::Gen9 {
|
||||
wa_write(wal, BLT_SEMA_WAIT_POLL, 1, "WaKBLVECSSemaphoreWaitPoll");
|
||||
}
|
||||
if matches!(gen, IntelGeneration::Gen12 | IntelGeneration::Gen12_7 | IntelGeneration::GenXe2) {
|
||||
wa_masked_field_set(wal, BLT_ECOSKPD, XEHP_BLITTER_SCHEDULING_MODE_MASK, XEHP_BLITTER_ROUND_ROBIN_MODE, "Wa_16018031267");
|
||||
}
|
||||
}
|
||||
|
||||
fn ccs_engine_wa_init(wal: &mut WorkaroundList, gen: IntelGeneration) {
|
||||
if gen == IntelGeneration::GenXe2 {
|
||||
wa_masked_en(wal, GEN12_RCU_MODE, XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE, "Wa_14019159160");
|
||||
wa_masked_en(wal, XEHP_CCS_MODE, 0x1, "XEHP_CCS_MODE_1");
|
||||
}
|
||||
}
|
||||
|
||||
fn engine_fake_wa_init(wal: &mut WorkaroundList, gen: IntelGeneration) {
|
||||
if matches!(gen, IntelGeneration::Gen12 | IntelGeneration::Gen12_7 | IntelGeneration::GenXe2) {
|
||||
wa_write_clr_set(wal, RING_CMD_CCTL, CMD_CCTL_MOCS_MASK, 0, "RING_CMD_CCTL_MOCS");
|
||||
}
|
||||
}
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
@@ -506,9 +656,9 @@ pub fn build_whitelist(device_info: &IntelDeviceInfo) -> WorkaroundList {
|
||||
info!("redox-drm-intel: building whitelist for {:?}", gen);
|
||||
|
||||
match gen {
|
||||
IntelGeneration::Gen9 | IntelGeneration::Gen9_5 => gen9_whitelist_build(&mut wal),
|
||||
IntelGeneration::Gen9 => gen9_whitelist_build(&mut wal),
|
||||
IntelGeneration::Gen9_5 => icl_whitelist_build(&mut wal),
|
||||
IntelGeneration::Gen12 => gen12_whitelist_build(&mut wal),
|
||||
IntelGeneration::Gen12 | IntelGeneration::Gen12_7 | IntelGeneration::GenXe2 => gen12_whitelist_build(&mut wal),
|
||||
_ => {}
|
||||
}
|
||||
|
||||
@@ -516,36 +666,38 @@ pub fn build_whitelist(device_info: &IntelDeviceInfo) -> WorkaroundList {
|
||||
}
|
||||
|
||||
fn gen9_whitelist_build(wal: &mut WorkaroundList) {
|
||||
// Gen9 whitelist: registers that userspace is allowed to access directly.
|
||||
wa_add(wal, 0xA2C0, 0, 0, 0, "GEN9_SLICE_COMMON_ECO_CHICKEN");
|
||||
wa_add(wal, 0x7018, 0, 0, 0, "GEN7_COMMON_SLICE_CHICKEN1");
|
||||
wa_add(wal, 0xB01C, 0, 0, 0, "GEN7_L3CNTLREG1");
|
||||
wa_add(wal, 0xB024, 0, 0, 0, "GEN7_L3_CHICKEN_MODE");
|
||||
wa_add(wal, 0xB034, 0, 0, 0, "GEN7_L3SQCREG4");
|
||||
wa_add(wal, 0x7300, 0, 0, 0, "GEN7_HALF_SLICE_CHICKEN1");
|
||||
wa_add(wal, 0x7304, 0, 0, 0, "GEN7_HALF_SLICE_CHICKEN2");
|
||||
wa_add(wal, 0xE4F0, 0, 0, 0, "GEN7_ROW_CHICKEN");
|
||||
wa_add(wal, 0xE180, 0, 0, 0, "GEN7_HALF_SLICE_CHICKEN");
|
||||
wa_add(wal, 0x7000, 0, 0, 0, "CACHE_MODE_0");
|
||||
wa_add(wal, 0x7004, 0, 0, 0, "CACHE_MODE_1");
|
||||
wa_add(wal, 0xB11C, 0, 0, 0, "GEN9_SAMPLER_MODE");
|
||||
wa_add(wal, GEN9_SLICE_COMMON_ECO_CHICKEN1, 0, 0, 0, "GEN9_SLICE_COMMON_ECO_CHICKEN");
|
||||
wa_add(wal, GEN7_COMMON_SLICE_CHICKEN1, 0, 0, 0, "GEN7_COMMON_SLICE_CHICKEN1");
|
||||
wa_add(wal, GEN7_L3CNTLREG1, 0, 0, 0, "GEN7_L3CNTLREG1");
|
||||
wa_add(wal, GEN7_L3_CHICKEN_MODE_REGISTER, 0, 0, 0, "GEN7_L3_CHICKEN_MODE");
|
||||
wa_add(wal, GEN7_L3SQCREG4, 0, 0, 0, "GEN7_L3SQCREG4");
|
||||
wa_add(wal, HDC_CHICKEN0, 0, 0, 0, "GEN7_HALF_SLICE_CHICKEN1");
|
||||
wa_add(wal, GEN7_COMMON_SLICE_CHICKEN3, 0, 0, 0, "GEN7_HALF_SLICE_CHICKEN2");
|
||||
wa_add(wal, GEN8_ROW_CHICKEN, 0, 0, 0, "GEN7_ROW_CHICKEN");
|
||||
wa_add(wal, HALF_SLICE_CHICKEN2, 0, 0, 0, "GEN7_HALF_SLICE_CHICKEN");
|
||||
wa_add(wal, CACHE_MODE_0_GEN7, 0, 0, 0, "CACHE_MODE_0");
|
||||
wa_add(wal, CACHE_MODE_1, 0, 0, 0, "CACHE_MODE_1");
|
||||
wa_add(wal, GEN8_SAMPLER_MODE, 0, 0, 0, "GEN9_SAMPLER_MODE");
|
||||
}
|
||||
|
||||
fn icl_whitelist_build(wal: &mut WorkaroundList) {
|
||||
gen9_whitelist_build(wal);
|
||||
// Gen11 additional whitelist entries.
|
||||
wa_add(wal, 0xA18C, 0, 0, 0, "GEN11_GT_SCRATCH");
|
||||
wa_add(wal, GEN11_GT_SCRATCH, 0, 0, 0, "GEN11_GT_SCRATCH");
|
||||
wa_add(wal, GEN9_HALF_SLICE_CHICKEN7, 0, 0, 0, "GEN9_HALF_SLICE_CHICKEN7");
|
||||
wa_add(wal, GEN10_SAMPLER_MODE, 0, 0, 0, "GEN10_SAMPLER_MODE");
|
||||
wa_add(wal, GEN9_SLICE_COMMON_ECO_CHICKEN1, 0, 0, 0, "GEN9_SLICE_COMMON_ECO_CHICKEN1_icl");
|
||||
}
|
||||
|
||||
fn gen12_whitelist_build(wal: &mut WorkaroundList) {
|
||||
gen9_whitelist_build(wal);
|
||||
// Gen12 additional whitelist entries.
|
||||
wa_add(wal, 0x55B0, 0, 0, 0, "GEN12_COMMON_SLICE_CHICKEN2");
|
||||
wa_add(wal, 0x7A10, 0, 0, 0, "GEN12_VF_PREEMPTION");
|
||||
wa_add(wal, 0x7A18, 0, 0, 0, "GEN12_VFLSKPD");
|
||||
wa_add(wal, 0x7A1C, 0, 0, 0, "GEN12_PSS_MODE2");
|
||||
wa_add(wal, 0x7A20, 0, 0, 0, "GEN12_PSS_CHICKEN");
|
||||
wa_add(wal, 0x7008, 0, 0, 0, "GEN12_CACHE_MODE_1");
|
||||
wa_add(wal, GEN12_COMMON_SLICE_CHICKEN2, 0, 0, 0, "GEN12_COMMON_SLICE_CHICKEN2");
|
||||
wa_add(wal, GEN12_VF_PREEMPTION, 0, 0, 0, "GEN12_VF_PREEMPTION");
|
||||
wa_add(wal, GEN12_VFLSKPD, 0, 0, 0, "GEN12_VFLSKPD");
|
||||
wa_add(wal, GEN12_PSS_MODE2, 0, 0, 0, "GEN12_PSS_MODE2");
|
||||
wa_add(wal, GEN12_PSS_CHICKEN, 0, 0, 0, "GEN12_PSS_CHICKEN");
|
||||
wa_add(wal, GEN12_CACHE_MODE_1, 0, 0, 0, "GEN12_CACHE_MODE_1");
|
||||
wa_add(wal, GEN11_COMMON_SLICE_CHICKEN3, 0, 0, 0, "GEN11_COMMON_SLICE_CHICKEN3");
|
||||
wa_add(wal, HIZ_CHICKEN, 0, 0, 0, "HIZ_CHICKEN");
|
||||
}
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
@@ -560,7 +712,7 @@ pub fn build_display_workarounds(device_info: &IntelDeviceInfo) -> WorkaroundLis
|
||||
|
||||
match gen {
|
||||
IntelGeneration::Gen9_5 => gen11_display_wa_init(&mut wal),
|
||||
IntelGeneration::Gen12 => gen12_display_wa_init(&mut wal),
|
||||
IntelGeneration::Gen12 | IntelGeneration::Gen12_7 | IntelGeneration::GenXe2 => gen12_display_wa_init(&mut wal),
|
||||
_ => {}
|
||||
}
|
||||
|
||||
@@ -568,13 +720,13 @@ pub fn build_display_workarounds(device_info: &IntelDeviceInfo) -> WorkaroundLis
|
||||
}
|
||||
|
||||
fn gen11_display_wa_init(wal: &mut WorkaroundList) {
|
||||
/* Wa_14010594013:icl */
|
||||
wa_masked_en(wal, GEN8_CHICKEN_DCPR_1, ICL_DELAY_PMRSP, "Wa_14010594013");
|
||||
}
|
||||
|
||||
fn gen12_display_wa_init(wal: &mut WorkaroundList) {
|
||||
/* Wa_14013723622:tgl */
|
||||
wa_write_clr(wal, CLKREQ_POLICY, CLKREQ_POLICY_MEM_UP_OVRD, "Wa_14013723622");
|
||||
wa_masked_en(wal, GEN9_CLKGATE_DIS_5, DPCE_GATING_DIS, "Wa_22011091694");
|
||||
wa_write_clr(wal, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, "Bspec_49189");
|
||||
}
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
Reference in New Issue
Block a user