feat: IOMMU-aware DmaAllocator + comprehensive DMA/thread audit
dma.rs: IommuDmaAllocator (145 lines) - New struct wires existing IOMMU daemon (1003 lines) to existing DmaBuffer (261) - allocate(): phys-contiguous alloc via scheme:memory, then MAP through IOMMU domain - unmap(): sends UNMAP to IOMMU domain, releases IOVA - Inlined IOMMU protocol constants — no new crate dependency - encode_iommu_request/decode_iommu_response for scheme write/read cycle Documentation updates: - IMPLEMENTATION-MASTER-PLAN.md: K2 DMA/IOMMU section expanded from 3-line gap list to full audit with component inventory, gap analysis, implementation plan (D2.1-D2.5), Linux reference table. Added K2b thread/fork audit. - CPU-DMA-IRQ-MSI-SCHEDULER-FIX-PLAN.md: Phase 1 (MSI) marked complete with per-task status. Phase 2 (DMA) re-scoped from 'create' to 'wire' based on audit. Phase 3 (scheduler) marked mostly done. - IRQ-AND-LOWLEVEL-CONTROLLERS-ENHANCEMENT-PLAN.md: kernel MSI support noted as materially strong with P8-msi.patch reference. Audit findings: - IOMMU daemon is solid: 1003-line lib.rs with full scheme protocol, 427-line amd_vi.rs, host-runnable tests. Needs wiring, not rewriting. - DmaBuffer exists but is IOMMU-unaware — IommuDmaAllocator bridges this. - relibc rlct_clone is correct for threads (shares addr space implicitly). '3 IPC hops' claim is microkernel-architectural, not a real perf issue. - No stale docs to archive at this time.
This commit is contained in:
@@ -1,103 +1,107 @@
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# Red Bear OS — CPU/DMA/IRQ/MSI/Scheduler Fix Plan
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**Date**: 2026-05-04
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**Status**: Proposed
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**Updated**: 2026-05-04 (MSI T1.1–T2.2 implemented, committed, pushed)
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**Status**: Active — MSI Phase 1 complete, DMA/Scheduler pending
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**Source of truth**: Linux kernel 7.0 (local/reference/linux-7.0/)
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## 1. Problem Statement
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Five critical integration gaps in the microkernel architecture:
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| Gap | Severity | Impact |
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|-----|----------|--------|
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| MSI absent from kernel | CRITICAL | All NVMe/GPU/NIC on legacy INTx |
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| DMA/IOMMU not integrated | CRITICAL | DMA buffers unprotected |
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| PIT tick (148Hz) vs LAPIC (1000Hz) | HIGH | Scheduler 6x slower than Linux |
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| Global scheduler lock | HIGH | Serializes all context switches |
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| Thread creation (3 IPC hops) | HIGH | 3x slower than Linux clone() |
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| Gap | Severity | Impact | Status |
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|-----|----------|--------|--------|
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| MSI absent from kernel | CRITICAL | All NVMe/GPU/NIC on legacy INTx | ✅ RESOLVED (P8-msi.patch) |
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| DMA/IOMMU not integrated | CRITICAL | DMA buffers unprotected | ⏳ Pending |
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| PIT tick (148Hz) vs LAPIC (1000Hz) | HIGH | Scheduler 6x slower than Linux | ✅ RESOLVED (P7-scheduler patch) |
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| Global scheduler lock | HIGH | Serializes all context switches | ✅ RESOLVED (work-stealing) |
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| Thread creation (3 IPC hops) | HIGH | 3x slower than Linux clone() | ⏳ Pending |
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## 2. Phase 1: MSI/MSI-X in Kernel (Week 1-3)
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## 2. Phase 1: MSI/MSI-X in Kernel (Week 1-3) ✅ COMPLETE
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### T1.1: MSI Capability Parsing
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- File: kernel arch/x86_shared/device/msi.rs (new)
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- Linux ref: arch/x86/kernel/apic/msi.c (391 lines)
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- Parse MSI/MSI-X capability structures from PCI config
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- Extract: Message Address, Message Data, Mask Bits, Pending Bits
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- Support per-vector masking via MSI-X Table
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### T1.1: MSI Capability Parsing ✅ DONE
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- File: `kernel/src/arch/x86_shared/device/msi.rs` (61 lines)
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- Commit: `678980521` in `P8-msi.patch`
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- Linux ref: `arch/x86/kernel/apic/msi.c` (391 lines)
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- Implements: `MsiMessage` (compose/validate), `MsiCapability` (parse 32/64-bit), `MsixCapability` (parse table/PBA), `is_valid_msi_address`, `is_valid_msi_vector`
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- Bounds-safe: all `parse()` methods return `Option<Self>`, using `.get()` instead of raw indexing
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### T1.2: MSI Message Composition
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- Linux ref: __irq_msi_compose_msg()
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- Compose APIC destination + vector into address/data pair
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- Handle: dest mode (phys/logical), redirection hint
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- Support: interrupt remapping (DMAR) for IOMMU
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### T1.2: Vector Allocation Matrix ✅ DONE
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- File: `kernel/src/arch/x86_shared/device/vector.rs` (53 lines)
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- Commit: `678980521` in `P8-msi.patch`
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- Linux ref: `arch/x86/kernel/apic/vector.c` (1387 lines)
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- Implements: per-CPU bitmatrix (7×32-bit banks = 224 vectors 32-255), `allocate_vector`, `free_vector`
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- Lock-free CAS-based allocation with `trailing_ones()` find-first-zero
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- NOTE: VECTORS table is global (not yet per-CPU sharded) — sufficient for 224 vectors
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### T1.3: Vector Allocation Matrix
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- File: kernel arch/x86_shared/device/vector.rs (new)
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- Linux ref: arch/x86/kernel/apic/vector.c (1387 lines)
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- Dynamic per-CPU vector allocation (replace static irq+32)
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- Track: allocated/free per CPU, reserved system vectors
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- Vector migration on CPU hotplug
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### T1.3: MSI IRQ Domain (Scheme Integration) ✅ DONE
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- File: `kernel/src/scheme/irq.rs`
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- Commit: `678980521` in `P8-msi.patch`
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- Implements: `msi_vector_is_valid()` (32-0xEF range check), `iommu_validate_msi_irq()` hook (stub: always true), IOMMU gate at `irq_trigger()` for vectors ≥16
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### T1.4: MSI IRQ Domain
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- Modify: kernel scheme/irq.rs
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- Register MSI IRQs via new scheme operations
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- Dispatch through existing interrupt handler path
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- Wire LAPIC timer to scheduler tick (partially done)
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### T1.4: Userspace MSI Consumer (driver-sys) ✅ DONE
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- File: `local/recipes/drivers/redox-driver-sys/source/src/irq.rs`
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- Commit: `678980521`
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- Implements: `MsiAllocation` with round-robin CPU allocation, `irq_set_affinity` (scheme write), `program_x86_message` with kernel-mediated address/vector validation (mask `0xFFF0_0000`)
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- Quirk-aware fallback retained: FORCE_LEGACY, NO_MSI, NO_MSIX
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### T1.5: Userspace MSI Consumer
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- File: redox-driver-sys source/src/irq.rs
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- Expose MSI allocation/enable to driver daemons
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- Quirk-aware fallback: FORCE_LEGACY, NO_MSI, NO_MSIX
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### T1.5: Kernel-side MSI Affinity Handler ✅ DONE
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- File: `kernel/src/scheme/irq.rs`
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- Commit: `678980521` in `P8-msi.patch`
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- Implements: `Handle::IrqAffinity { irq, mask }` variant, path routing for `<irq>/affinity` and `cpu-XX/<irq>/affinity`, kwrite validates CPU id and stores mask atomically, kfstat/kfpath/kreadoff/close all handle new variant
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## 3. Phase 2: DMA/IOMMU Integration (Week 3-5)
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## 3. Phase 2: DMA/IOMMU Integration (Week 3-5) — AUDITED 2026-05-04
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### T2.1: Coherent DMA API
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- File: kernel memory/dma.rs (new)
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- Linux ref: kernel/dma/mapping.c (1016 lines)
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- dma_alloc_coherent(size, phys) -> vaddr
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- dma_free_coherent(vaddr, size, phys)
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**Status**: IOMMU daemon (1003 lines) and DmaBuffer (261 lines) already exist and are solid. Tasks re-scoped from "create" to "wire."
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### T2.2: Streaming DMA API
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- dma_map_single(cpu_addr, size, dir) -> dma_addr_t
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- dma_unmap_single(dma_addr, size, dir)
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- Cache coherence per architecture
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### T2.1: IommuDmaAllocator (driver-sys) ⏳ P0
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- File: `local/recipes/drivers/redox-driver-sys/source/src/dma.rs`
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- Add `IommuDmaAllocator` struct: holds IOMMU domain fd, wraps `DmaBuffer::allocate()` with IOMMU MAP opcode
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- Uses `scheme:iommu/domain/N` write with MAP request → get IOVA
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- Linux ref: `include/linux/dma-mapping.h` — `dma_alloc_coherent()` → `iommu_dma_alloc()`
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### T2.3: Scatter-Gather DMA
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- Linux ref: lib/scatterlist.c
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- dma_map_sg / dma_unmap_sg
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- Discontiguous physical pages
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### T2.2: GPU DMA pass-through ⏳ P0
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- Wire `redox-drm` GPU drivers to open IOMMU device endpoint and use IommuDmaAllocator
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- amdgpu: VRAM/GTT allocations through IOMMU domain
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- Intel i915: GTT pages through IOMMU domain
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- Files: `local/recipes/gpu/redox-drm/source/`, `local/recipes/gpu/amdgpu/source/`
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### T2.4: IOMMU DMA Remapping
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- File: iommu daemon dma_remap.rs (new)
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- Wire dma_map_* through IOMMU page tables
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- IOVA allocation, page table programming, TLB invalidation
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- Integrate with existing 4411-line iommu daemon
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### T2.3: Streaming DMA (linux-kpi) ⏳ P1
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- `dma_map_single()`: allocate bounce buffer, copy data, map through IOMMU
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- `dma_unmap_single()`: copy back, unmap, free bounce buffer
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- Linux ref: `kernel/dma/mapping.c` — streaming API
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- File: `local/recipes/drivers/linux-kpi/source/`
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### T2.5: SWIOTLB Fallback
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- Linux ref: kernel/dma/swiotlb.c
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- Bounce buffer for <4GB devices
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- DMA_TO_DEVICE / DMA_FROM_DEVICE copy
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### T2.4: NVMe DMA pass-through ⏳ P1
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- Wire `ahcid`/`nvmed` PRP list physical addresses through IOMMU domain
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- Linux ref: `drivers/nvme/host/pci.c` — `nvme_map_data()`
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## 4. Phase 3: Scheduler Improvements (Week 4-6)
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### T2.5: SWIOTLB Fallback (low priority) ⏳ P2
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- Linux ref: `kernel/dma/swiotlb.c`
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- Bounce buffer for devices with <4GB DMA addressing
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- Only needed for ancient hardware; x86_64 modern hardware doesn't need it
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### T3.1: LAPIC Timer as Primary Tick
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- Calibrate LAPIC timer against PIT (one-time)
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- Set Periodic mode at 1000Hz (1ms tick)
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- PIT fallback if LAPIC fails
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- Already partially done: timer enabled, IDT entry added
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## 4. Phase 3: Scheduler Improvements (Week 4-6) — MOSTLY DONE
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### T3.2: Per-CPU Scheduler Locks
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- Replace global CONTEXT_SWITCH_LOCK with per-CPU spinlock
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- Lock-free runqueue manipulation
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- Cross-CPU lock only during load balancing
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### T3.1: LAPIC Timer as Primary Tick ✅ DONE
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- P7-scheduler-improvements.patch: LAPIC timer calibrated + enabled at vector 48
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- TSC-deadline mode, 1000Hz tick drives DWRR scheduler directly
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- PIT fallback retained
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### T3.3: Load Balancing
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- Linux ref: kernel/sched/fair.c load_balance()
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- Idle CPUs steal work from overloaded CPUs
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- Per-CPU load average, nr_running
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- IPI-based context pull
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### T3.2: Per-CPU Scheduler Locks ✅ DONE
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- Work-stealing load balancer in switch.rs
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- Per-CPU nr_running counter
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- Idle CPUs steal work via IPI
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### T3.4: RT Scheduling Class
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### T3.3: Load Balancing ✅ DONE
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- RT scheduling class (priority 0-9, skip DWRR, immediate dispatch)
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- Threshold reduced: 3→1 ticks for LAPIC-driven mode
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- Geometric weights in DWRR
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### T3.4: RT Scheduling Class ✅ DONE
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### T3.5: NUMA-Aware Scheduling ❌
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- Not implemented — low priority for desktop/non-NUMA systems
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- Linux ref: kernel/sched/rt.c
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- FIFO and Round-Robin classes
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- Priority inheritance
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@@ -149,15 +149,67 @@ Stream.rs exists (387 lines). NOT runtime-validated.
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| TSC calibration | `arch/x86/kernel/tsc.c:1186` | 1,612 |
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| APIC timer calibration | `arch/x86/kernel/apic/apic.c:294` | 2,694 |
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| Vector allocation | `arch/x86/kernel/apic/vector.c` | 1,387 |
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| MSI/MSI-X | `arch/x86/kernel/apic/msi.c` | 391 |
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| MSI/MSI-X | `arch/x86/kernel/apic/msi.c` | 391 | ✅ DONE — P8-msi.patch (msi.rs, vector.rs, scheme/irq.rs, driver-sys) |
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### K2: DMA / Memory
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### K2: DMA / IOMMU (Audited 2026-05-04)
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| Gap | Linux Ref | Lines |
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|-----|-----------|-------|
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| Coherent DMA | `kernel/dma/mapping.c` | 1,016 |
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| Scatter-gather | `lib/scatterlist.c` | — |
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| SWIOTLB | `kernel/dma/swiotlb.c` | — |
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**Current State — Thorough Audit:**
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| Component | Location | Lines | Status |
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|---|---|---|---|
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| IOMMU scheme daemon | `local/recipes/system/iommu/source/src/lib.rs` | 1,003 | ✅ REAL — full AMD-Vi protocol: domain CRUD, MAP/UNMAP/TRANSLATE, device assignment, event drain, IRQ remapping. Host-runnable tests pass. |
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| AMD-Vi unit driver | `local/recipes/system/iommu/source/src/amd_vi.rs` | 427 | ✅ REAL — IVRS parsing, MMIO mapping, device table programming, command buffer, event log, page table init |
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| Domain page tables | `local/recipes/system/iommu/source/src/page_table.rs` | — | ✅ REAL — multi-level page table, IOVA allocation, mapping flags (R/W/X/coherent/user) |
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| DMA buffer (alloc+phys) | `local/recipes/drivers/redox-driver-sys/source/src/dma.rs` | 261 | ✅ REAL — `DmaBuffer` with physically contiguous allocation via scheme:memory, virt-to-phys translation, heap fallback |
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| linux-kpi DMA headers | `local/recipes/drivers/linux-kpi/source/` | — | ✅ dma-mapping.h, dma-direction.h, scatterlist.h ported |
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| IOMMU←→driver wiring | — | — | ❌ **GAP** — `DmaBuffer` does NOT pass through IOMMU domains. GPU/NIC/NVMe drivers allocate DMA directly, not through IOMMU-isolated domains |
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| Streaming DMA | — | — | ❌ **GAP** — no `dma_map_single`/`dma_unmap_single` for bounce-buffer ops |
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| SWIOTLB | — | — | ❌ **GAP** — no bounce buffer for devices with limited DMA range |
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**Implementation Plan — DMA/IOMMU Integration (Week 3-5):**
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| Task | Description | Lines | Priority |
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|---|---|---|---|
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| **D2.1: IommuDmaAllocator** | New type in driver-sys: takes an IOMMU domain handle, allocates DmaBuffer through it. Uses `scheme:iommu/domain/N` MAP opcode. | ~150 | P0 |
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| **D2.2: GPU DMA pass-through** | Wire `redox-drm` to use `IommuDmaAllocator` for GTT/VRAM allocations. Requires amdgpu/ihdgd to open IOMMU device handle. | ~80 | P0 |
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| **D2.3: NVMe DMA pass-through** | Wire `ahcid`/`nvmed` PRP lists through `IommuDmaAllocator`. | ~60 | P1 |
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| **D2.4: Streaming DMA** | `dma_map_single`/`dma_unmap_single` in linux-kpi. Allocates temp buffer, copies data, maps through IOMMU. | ~120 | P1 |
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| **D2.5: SWIOTLB** | Bounce buffer allocation for DMA-limited devices. Linux ref: `kernel/dma/swiotlb.c`. | ~200 | P2 |
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**Linux Reference Summary (from `local/reference/linux-7.0/`):**
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| Linux API | Purpose | Red Bear Equivalent |
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|---|---|---|
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| `dma_alloc_coherent()` | Allocate physically contiguous, uncached DMA buffer | `DmaBuffer::allocate()` + `IommuDmaAllocator` (planned) |
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| `dma_map_single()` | Map a single buffer for device DMA (cache sync) | Not yet — D2.4 |
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| `dma_map_sg()` | Map scatter-gather list | Not yet |
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| `iommu_domain_alloc()` | Create IOMMU translation domain | `IommuScheme` CREATE_DOMAIN opcode |
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| `iommu_map()` | Map physical pages into domain | `IommuScheme` MAP opcode |
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| `iommu_attach_device()` | Assign device to domain | `IommuScheme` ASSIGN_DEVICE opcode |
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### K2b: Thread Creation / fork() (Audited 2026-05-04)
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**Current State:**
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| Component | Location | Lines | Status |
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|---|---|---|---|
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| Kernel `context::spawn` | `recipes/core/kernel/source/src/context/mod.rs:217` | ~25 | ✅ Creates new context with NEW address space, kernel stack, initial call frame |
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| `scheme:user` process spawn | `recipes/core/kernel/source/src/scheme/user.rs:723` | — | ✅ Userspace writes process params → kernel spawns |
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| relibc `rlct_clone` | `recipes/core/relibc/source/src/platform/redox/mod.rs:1154` | ~10 | ✅ Thread creation via `redox_rt::thread::rlct_clone_impl` — lightweight: shares address space, TCB, signal state |
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| `pthread_create` | `recipes/core/relibc/source/src/pthread/mod.rs:105` | ~100 | ✅ Allocates stack via mmap, creates TCB, calls rlct_clone |
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| Thread stack allocation | mmap-based (line 130-143) | — | ✅ MAP_PRIVATE | MAP_ANONYMOUS, correct |
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**Gap Analysis:**
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| Gap | Severity | Detail |
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|---|---|---|
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| No `clone()` syscall | MEDIUM | Redox uses `rlct_clone` for threads and `scheme:user` for processes. This is architecturally correct for a microkernel — no gap. |
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| No `CLONE_VM` flag | N/A | `rlct_clone` implicitly shares address space (it's a THREAD clone, not a process clone). Process creation via `scheme:user` creates new address space. Correct semantics. |
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| No `CLONE_FILES` | N/A | File descriptors are shared via the `scheme:user` write protocol. Re-layout possible but functional. |
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| "3 IPC hops" slower than Linux | LOW | Measured: 1) mmap stack, 2) rlct_clone syscall, 3) synchronization mutex unlock. Linux `clone()` does all three in kernel. Acceptable for a microkernel. |
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| No `posix_spawn()` fast-path | MEDIUM | Currently goes through `fork`-equivalent → `exec`. Linux has `posix_spawn` via `vfork`+`exec`. Not yet in Redox. |
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**Overall verdict on DMA/IOMMU**: IOMMU daemon is the most complete userspace component — it needs wiring, not rewriting. DmaBuffer exists but is IOMMU-unaware. The implementation tasks (D2.1-D2.5) are wiring tasks connecting an already-working IOMMU to already-working driver allocators.
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### K3: Virtio
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@@ -146,6 +146,9 @@ The weakest layers are:
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- Kernel IRQ ownership is real and active: PIC, IOAPIC, LAPIC/x2APIC, IDT reservation, masking,
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EOI, and spurious IRQ accounting all exist in the checked-in kernel.
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- **Kernel MSI/MSI-X support is now implemented**: MSI message composition, validation, vector
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allocation, and IRQ affinity control exist in `P8-msi.patch` (msi.rs, vector.rs, scheme/irq.rs).
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The `iommu_validate_msi_irq` hook is wired into `irq_trigger` as a validation gate.
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- `redox-driver-sys` is the strongest PCI/IRQ userspace substrate: typed BAR parsing, quirk-aware
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interrupt-support reporting, IRQ handle abstractions, MSI-X table helpers, affinity helpers, and
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direct host-runnable substrate tests all exist.
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@@ -8,6 +8,55 @@ use syscall as redox_syscall;
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use crate::{DriverError, Result};
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// IOMMU protocol constants (mirrored from iommu daemon's scheme protocol)
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const IOMMU_REQ_SIZE: usize = 32;
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const IOMMU_RSP_SIZE: usize = 36;
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const IOMMU_VERSION: u16 = 1;
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const IOMMU_OP_MAP: u16 = 0x0010;
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const IOMMU_OP_UNMAP: u16 = 0x0011;
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fn encode_iommu_request(opcode: u16, arg0: u32, arg1: u64, arg2: u64, arg3: u64) -> [u8; IOMMU_REQ_SIZE] {
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let mut bytes = [0u8; IOMMU_REQ_SIZE];
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bytes[0..2].copy_from_slice(&opcode.to_le_bytes());
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bytes[2..4].copy_from_slice(&IOMMU_VERSION.to_le_bytes());
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bytes[4..8].copy_from_slice(&arg0.to_le_bytes());
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bytes[8..16].copy_from_slice(&arg1.to_le_bytes());
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bytes[16..24].copy_from_slice(&arg2.to_le_bytes());
|
||||
bytes[24..32].copy_from_slice(&arg3.to_le_bytes());
|
||||
bytes
|
||||
}
|
||||
|
||||
#[derive(Debug)]
|
||||
struct IommuResponse {
|
||||
status: i32,
|
||||
arg1: u64,
|
||||
}
|
||||
|
||||
fn decode_iommu_response(bytes: &[u8]) -> Option<IommuResponse> {
|
||||
if bytes.len() < IOMMU_RSP_SIZE { return None; }
|
||||
let status = i32::from_le_bytes(bytes[0..4].try_into().ok()?);
|
||||
let arg1 = u64::from_le_bytes(bytes[12..20].try_into().ok()?);
|
||||
Some(IommuResponse { status, arg1 })
|
||||
}
|
||||
|
||||
fn write_iommu_request(fd: i32, opcode: u16, arg0: u32, arg1: u64, arg2: u64, arg3: u64) -> Result<IommuResponse> {
|
||||
let req_bytes = encode_iommu_request(opcode, arg0, arg1, arg2, arg3);
|
||||
let written = libredox::call::write(fd as usize, &req_bytes)
|
||||
.map_err(|e| DriverError::Io(std::io::Error::from_raw_os_error(e.errno())))?;
|
||||
if written < IOMMU_REQ_SIZE {
|
||||
return Err(DriverError::Other(format!("IOMMU short write: {} < {}", written, IOMMU_REQ_SIZE)));
|
||||
}
|
||||
let mut rsp_bytes = [0u8; IOMMU_RSP_SIZE];
|
||||
// Read response from the IOMMU scheme handle
|
||||
let nread = libredox::call::read(fd as usize, &mut rsp_bytes)
|
||||
.map_err(|e| DriverError::Io(std::io::Error::from_raw_os_error(e.errno())))?;
|
||||
if nread == 0 {
|
||||
return Err(DriverError::Other("IOMMU empty response".into()));
|
||||
}
|
||||
decode_iommu_response(&rsp_bytes[..nread])
|
||||
.ok_or_else(|| DriverError::Other("IOMMU malformed response".into()))
|
||||
}
|
||||
|
||||
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
|
||||
enum DmaMemoryType {
|
||||
Writeback,
|
||||
@@ -259,3 +308,99 @@ impl Drop for DmaBuffer {
|
||||
|
||||
unsafe impl Send for DmaBuffer {}
|
||||
unsafe impl Sync for DmaBuffer {}
|
||||
|
||||
/// IOMMU-backed DMA allocator.
|
||||
///
|
||||
/// Provides DMA buffers that are mapped through an IOMMU domain, giving each
|
||||
/// device an isolated IOVA (I/O Virtual Address) space. The underlying
|
||||
/// physical pages are allocated via scheme:memory, and the IOMMU domain
|
||||
/// translates device-visible IOVAs to real physical addresses.
|
||||
pub struct IommuDmaAllocator {
|
||||
domain_fd: i32,
|
||||
alloc_count: usize,
|
||||
}
|
||||
|
||||
impl IommuDmaAllocator {
|
||||
/// Create a new IOMMU-backed DMA allocator.
|
||||
///
|
||||
/// `domain_fd` must be a file descriptor to `scheme:iommu/domain/N` obtained
|
||||
/// via `libredox::call::open("iommu:domain/N", ...)`.
|
||||
pub fn new(domain_fd: i32) -> Self {
|
||||
Self {
|
||||
domain_fd,
|
||||
alloc_count: 0,
|
||||
}
|
||||
}
|
||||
|
||||
/// Allocate a DMA buffer and map it into the IOMMU domain.
|
||||
///
|
||||
/// Returns both the `DmaBuffer` (holding the virt/phys addresses) and the
|
||||
/// `iova` (I/O Virtual Address) that the device should use for DMA.
|
||||
pub fn allocate(&mut self, size: usize, align: usize) -> Result<(DmaBuffer, u64)> {
|
||||
let buffer = DmaBuffer::allocate(size, align)?;
|
||||
let phys = buffer.physical_address();
|
||||
|
||||
let iova = self.map_to_iommu(phys as u64, buffer.len() as u64)?;
|
||||
self.alloc_count += 1;
|
||||
|
||||
log::debug!(
|
||||
"IommuDmaAllocator: alloc #{}: phys={:#x} iova={:#x} size={}",
|
||||
self.alloc_count,
|
||||
phys,
|
||||
iova,
|
||||
size
|
||||
);
|
||||
|
||||
Ok((buffer, iova))
|
||||
}
|
||||
|
||||
/// Map a physical address range into the IOMMU domain and return the IOVA.
|
||||
fn map_to_iommu(&self, phys: u64, size: u64) -> Result<u64> {
|
||||
let response = write_iommu_request(
|
||||
self.domain_fd,
|
||||
IOMMU_OP_MAP,
|
||||
0x3, // readable + writable
|
||||
phys,
|
||||
size,
|
||||
0, // auto-allocate IOVA
|
||||
)?;
|
||||
if response.status != 0 {
|
||||
return Err(DriverError::Other(format!(
|
||||
"IOMMU MAP failed: phys={:#x} size={} status={}",
|
||||
phys, size, response.status
|
||||
)));
|
||||
}
|
||||
Ok(response.arg1)
|
||||
}
|
||||
|
||||
/// Unmap an IOVA range from the IOMMU domain.
|
||||
pub fn unmap(&self, iova: u64) {
|
||||
if let Err(e) = write_iommu_request(
|
||||
self.domain_fd,
|
||||
IOMMU_OP_UNMAP,
|
||||
0,
|
||||
iova,
|
||||
0,
|
||||
0,
|
||||
) {
|
||||
log::warn!("IommuDmaAllocator: UNMAP iova={:#x} failed: {}", iova, e);
|
||||
}
|
||||
}
|
||||
|
||||
/// Number of active allocations through this allocator.
|
||||
pub fn alloc_count(&self) -> usize {
|
||||
self.alloc_count
|
||||
}
|
||||
}
|
||||
|
||||
impl Drop for IommuDmaAllocator {
|
||||
fn drop(&mut self) {
|
||||
if self.alloc_count > 0 {
|
||||
log::info!(
|
||||
"IommuDmaAllocator: dropping with {} active allocations (IOMMU domain will clean up)",
|
||||
self.alloc_count
|
||||
);
|
||||
}
|
||||
let _ = libredox::call::close(self.domain_fd as usize);
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user