Remove unnecessary unsafe declarations.

The removed unsafe statements were identified by rustc as unneeded during
compilation.

Signed-off-by: Wren Turkal <wt@penguintechs.org>

ihdad/src/hda/device.rs

@@ -153,26 +153,23 @@ impl IntelHDA {
 	pub unsafe fn new(base: usize, vend_prod:u32) -> Result<Self> {
 		let regs = &mut *(base as *mut Regs);
 
-		let buff_desc_phys = unsafe {
+		let buff_desc_phys =
 			syscall::physalloc(0x1000)
-				.expect("Could not allocate physical memory for buffer descriptor list.")
-		};
+				.expect("Could not allocate physical memory for buffer descriptor list.");
 
-		let buff_desc_virt = unsafe {
+		let buff_desc_virt =
 			syscall::physmap(buff_desc_phys, 0x1000, PHYSMAP_WRITE | PHYSMAP_NO_CACHE)
-				.expect("ihdad: failed to map address for buffer descriptor list.")
-		};
+				.expect("ihdad: failed to map address for buffer descriptor list.");
 
 		print!("Virt: {:016X}, Phys: {:016X}\n", buff_desc_virt, buff_desc_phys);
 
 		let buff_desc = &mut *(buff_desc_virt as *mut [BufferDescriptorListEntry;256]);
 
-		let cmd_buff_address = unsafe {
+		let cmd_buff_address =
 			syscall::physalloc(0x1000)
-				.expect("Could not allocate physical memory for CORB and RIRB.")
-		};
+				.expect("Could not allocate physical memory for CORB and RIRB.");
 
-		let cmd_buff_virt = unsafe { syscall::physmap(cmd_buff_address, 0x1000, PHYSMAP_WRITE | PHYSMAP_NO_CACHE).expect("ihdad: failed to map address for CORB/RIRB buff") };
+		let cmd_buff_virt = syscall::physmap(cmd_buff_address, 0x1000, PHYSMAP_WRITE | PHYSMAP_NO_CACHE).expect("ihdad: failed to map address for CORB/RIRB buff");
 
 		print!("Virt: {:016X}, Phys: {:016X}\n", cmd_buff_virt, cmd_buff_address);
 		let mut module = IntelHDA {

ihdad/src/hda/stream.rs

@@ -209,12 +209,10 @@ pub struct OutputStream {
 
 impl OutputStream {
 	pub fn new(block_count: usize, block_length: usize, regs: &'static mut StreamDescriptorRegs) -> OutputStream {
-		unsafe {
-			OutputStream {
-				buff: StreamBuffer::new(block_length, block_count).unwrap(),
+		OutputStream {
+			buff: StreamBuffer::new(block_length, block_count).unwrap(),
 
-				desc_regs: regs,
-			}
+			desc_regs: regs,
 		}
 	}
 

ihdad/src/main.rs

@@ -77,7 +77,7 @@ fn main() {
 				let mut irq = [0; 8];
 				irq_file.read(&mut irq)?;
 
-				if unsafe { device_irq.borrow_mut().irq() } {
+				if device_irq.borrow_mut().irq() {
 					irq_file.write(&mut irq)?;
 
 					let mut todo = todo_irq.borrow_mut();

ixgbed/src/device.rs

@@ -75,10 +75,8 @@ impl SchemeBlockMut for Intel8259x {
             let i = cmp::min(buf.len(), data.len());
             buf[..i].copy_from_slice(&data[..i]);
 
-            unsafe {
                 desc.read.pkt_addr = self.receive_buffer[self.receive_index].physical() as u64;
                 desc.read.hdr_addr = 0;
-            }
 
             self.write_reg(IXGBE_RDT(0), self.receive_index as u32);
             self.receive_index = wrap_ring(self.receive_index, self.receive_ring.len());
@@ -131,7 +129,6 @@ impl SchemeBlockMut for Intel8259x {
         let i = cmp::min(buf.len(), data.len());
         data[..i].copy_from_slice(&buf[..i]);
 
-        unsafe {
             desc.read.cmd_type_len = IXGBE_ADVTXD_DCMD_EOP
                 | IXGBE_ADVTXD_DCMD_RS
                 | IXGBE_ADVTXD_DCMD_IFCS
@@ -140,7 +137,6 @@ impl SchemeBlockMut for Intel8259x {
                 | buf.len() as u32;
 
             desc.read.olinfo_status = (buf.len() as u32) << IXGBE_ADVTXD_PAYLEN_SHIFT;
-        }
 
         self.transmit_index = wrap_ring(self.transmit_index, self.transmit_ring.len());
         self.transmit_ring_free -= 1;
@@ -506,10 +502,8 @@ impl Intel8259x {
         }
 
         for i in 0..self.receive_ring.len() {
-            unsafe {
-                self.receive_ring[i].read.pkt_addr = self.receive_buffer[i].physical() as u64;
-                self.receive_ring[i].read.hdr_addr = 0;
-            }
+            self.receive_ring[i].read.pkt_addr = self.receive_buffer[i].physical() as u64;
+            self.receive_ring[i].read.hdr_addr = 0;
         }
 
         // enable queue and wait if necessary
@@ -536,9 +530,7 @@ impl Intel8259x {
         }
 
         for i in 0..self.transmit_ring.len() {
-            unsafe {
-                self.transmit_ring[i].read.buffer_addr = self.transmit_buffer[i].physical() as u64;
-            }
+            self.transmit_ring[i].read.buffer_addr = self.transmit_buffer[i].physical() as u64;
         }
 
         // tx queue starts out empty

ixgbed/src/main.rs

@@ -95,10 +95,10 @@ fn main() {
                 .expect("ixgbed: failed to map address")
         };
         {
-            let device = Arc::new(RefCell::new(unsafe {
+            let device = Arc::new(RefCell::new(
                 device::Intel8259x::new(address, IXGBE_MMIO_SIZE)
                     .expect("ixgbed: failed to allocate device")
-            }));
+            ));
 
             let mut event_queue =
                 EventQueue::<usize>::new().expect("ixgbed: failed to create event queue");
@@ -116,7 +116,7 @@ fn main() {
                     move |_event| -> Result<Option<usize>> {
                         let mut irq = [0; 8];
                         irq_file.read(&mut irq)?;
-                        if unsafe { device_irq.borrow().irq() } {
+                        if device_irq.borrow().irq() {
                             irq_file.write(&irq)?;
 
                             if handle_update(