vasilito
cb424d7448
verify-patch-sanity.py validates every active recipe .patch has internally- consistent hunk line counts — catching the 'malformed patch at line N' failure at commit/CI/preflight time instead of hours into a cook. This cycle hit that class three times (qtwaylandscanner, sddm, xwayland), each only discovered when cookbook tried to apply the patch. Running it across the repo found 29 latent malformed patches (validated against GNU patch: e.g. relibc/P3-sysv-ipc reproduces 'malformed patch at line 22'). They were harmless only because they sit in vendored recipes (baked, not re- applied) — but would fail on any version-bump re-derivation. --fix recounts the hunk headers (body untouched) and repaired all 29. Wired into build-preflight.sh (Phase 1.0D) and redbear-ci.yml, with a unit test (test-patch-sanity.sh). Skips archived/legacy trees and unvalidatable formats (empty placeholders, bare-@@ git hunks).
97 lines
2.8 KiB
TableGen
97 lines
2.8 KiB
TableGen
// RUN: llvm-tblgen %s | FileCheck %s
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// XFAIL: vg_leak
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// CHECK: add_ps
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// CHECK: add_ps
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// CHECK: add_ps
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// CHECK-NOT: add_ps
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class ValueType<int size, int value> {
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int Size = size;
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int Value = value;
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}
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def v2i64 : ValueType<128, 22>; // 2 x i64 vector value
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def v2f64 : ValueType<128, 28>; // 2 x f64 vector value
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class Intrinsic<string name> {
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string Name = name;
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}
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class Inst<bits<8> opcode, dag oopnds, dag iopnds, string asmstr,
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list<dag> pattern> {
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bits<8> Opcode = opcode;
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dag OutOperands = oopnds;
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dag InOperands = iopnds;
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string AssemblyString = asmstr;
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list<dag> Pattern = pattern;
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}
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def ops;
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def outs;
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def ins;
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def set;
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// Define registers
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class Register<string n> {
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string Name = n;
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}
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class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
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list<ValueType> RegTypes = regTypes;
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list<Register> MemberList = regList;
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}
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def XMM0: Register<"xmm0">;
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def XMM1: Register<"xmm1">;
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def XMM2: Register<"xmm2">;
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def XMM3: Register<"xmm3">;
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def XMM4: Register<"xmm4">;
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def XMM5: Register<"xmm5">;
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def XMM6: Register<"xmm6">;
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def XMM7: Register<"xmm7">;
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def XMM8: Register<"xmm8">;
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def XMM9: Register<"xmm9">;
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def XMM10: Register<"xmm10">;
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def XMM11: Register<"xmm11">;
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def XMM12: Register<"xmm12">;
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def XMM13: Register<"xmm13">;
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def XMM14: Register<"xmm14">;
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def XMM15: Register<"xmm15">;
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def VR128 : RegisterClass<[v2i64, v2f64],
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[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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XMM8, XMM9, XMM10, XMM11,
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XMM12, XMM13, XMM14, XMM15]>;
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// Define intrinsics
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def int_x86_sse2_add_ps : Intrinsic<"addps">;
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def int_x86_sse2_add_pd : Intrinsic<"addpd">;
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multiclass arith<bits<8> opcode, string asmstr, string Intr> {
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def PS : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
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!strconcat(asmstr, "\t$dst, $src1, $src2"),
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[(set VR128:$dst, (!cast<Intrinsic>(!strconcat(Intr, "_ps")) VR128:$src1, VR128:$src2))]>;
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def PD : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
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!strconcat(asmstr, "\t$dst, $src1, $src2"),
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[(set VR128:$dst, (!cast<Intrinsic>(!strconcat(Intr, "_pd")) VR128:$src1, VR128:$src2))]>;
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}
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defm ADD : arith<0x58, "add", "int_x86_sse2_add">;
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class IntInst<bits<8> opcode, string asmstr, Intrinsic Intr> :
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Inst<opcode,(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
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!strconcat(asmstr, "\t$dst, $src1, $src2"),
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[(set VR128:$dst, (Intr VR128:$src1, VR128:$src2))]>;
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multiclass arith_int<bits<8> opcode, string asmstr, string Intr> {
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def PS_Int : IntInst<opcode, asmstr, !cast<Intrinsic>(!strconcat(Intr, "_ps"))>;
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def PD_Int : IntInst<opcode, asmstr, !cast<Intrinsic>(!strconcat(Intr, "_pd"))>;
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}
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defm ADD : arith_int<0x58, "add", "int_x86_sse2_add">;
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