vasilito
cb424d7448
verify-patch-sanity.py validates every active recipe .patch has internally- consistent hunk line counts — catching the 'malformed patch at line N' failure at commit/CI/preflight time instead of hours into a cook. This cycle hit that class three times (qtwaylandscanner, sddm, xwayland), each only discovered when cookbook tried to apply the patch. Running it across the repo found 29 latent malformed patches (validated against GNU patch: e.g. relibc/P3-sysv-ipc reproduces 'malformed patch at line 22'). They were harmless only because they sit in vendored recipes (baked, not re- applied) — but would fail on any version-bump re-derivation. --fix recounts the hunk headers (body untouched) and repaired all 29. Wired into build-preflight.sh (Phase 1.0D) and redbear-ci.yml, with a unit test (test-patch-sanity.sh). Skips archived/legacy trees and unvalidatable formats (empty placeholders, bare-@@ git hunks).
68 lines
2.0 KiB
TableGen
68 lines
2.0 KiB
TableGen
// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
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// Test to check the bare minimum pressure sets.
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// At least one register pressure set is required for the target.
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// Allowed the pset only for D_32 regclass and ignored it for all
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// other classes including the tuples.
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include "llvm/Target/Target.td"
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class MyClass<int size, list<ValueType> types, dag registers>
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: RegisterClass<"MyTarget", types, size, registers> {
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let Size = size;
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}
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def sub0 : SubRegIndex<32>;
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def sub1 : SubRegIndex<32, 32>;
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let Namespace = "MyTarget" in {
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def D : Register<"d">;
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foreach Index = 0-7 in {
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def S#Index : Register <"s"#Index>;
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}
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}
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// Should generate psets for D_32
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def D_32 : MyClass<32, [i32], (add D)>;
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let GeneratePressureSet = 0 in {
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def S_32 : MyClass<32, [i32], (sequence "S%u", 0, 7)>;
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def SD_32 : MyClass<32, [i32], (add S_32, D_32)>;
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}
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def S_64 : RegisterTuples<[sub0, sub1],
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[(decimate (shl S_32, 0), 1),
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(decimate (shl S_32, 1), 1)
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]>;
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def SReg_64 : MyClass<64, [i64], (add S_64)> {
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let GeneratePressureSet = 0;
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}
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def MyTarget : Target;
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// CHECK-LABEL: // Register pressure sets enum.
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// CHECK-NEXT: namespace MyTarget {
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// CHECK-NEXT: enum RegisterPressureSets {
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// CHECK-NEXT: D_32 = 0,
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// CHECK-NEXT: };
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// NAMESPACE-NEXT: } // end namespace TestNamespace
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// CHECK-LABEL: getRegPressureSetName(unsigned Idx) const {
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// CHECK-NEXT: static const char *PressureNameTable[] = {
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// CHECK-NEXT: "D_32",
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// CHECK-NEXT: };
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// CHECK-NEXT: return PressureNameTable[Idx];
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// CHECK-NEXT: }
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// CHECK: unsigned MyTargetGenRegisterInfo::
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// CHECK-NEXT: getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
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// CHECK-NEXT: static const uint8_t PressureLimitTable[] = {
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// CHECK-NEXT: {{[0-9]+}}, // 0: D_32
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// CHECK-NEXT: };
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// CHECK-NEXT: return PressureLimitTable[Idx];
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// CHECK-NEXT:}
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// CHECK: static const int RCSetsTable[] = {
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// CHECK-NEXT: /* 0 */ 0, -1,
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// CHECK-NEXT: };
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