vasilito
cb424d7448
verify-patch-sanity.py validates every active recipe .patch has internally- consistent hunk line counts — catching the 'malformed patch at line N' failure at commit/CI/preflight time instead of hours into a cook. This cycle hit that class three times (qtwaylandscanner, sddm, xwayland), each only discovered when cookbook tried to apply the patch. Running it across the repo found 29 latent malformed patches (validated against GNU patch: e.g. relibc/P3-sysv-ipc reproduces 'malformed patch at line 22'). They were harmless only because they sit in vendored recipes (baked, not re- applied) — but would fail on any version-bump re-derivation. --fix recounts the hunk headers (body untouched) and repaired all 29. Wired into build-preflight.sh (Phase 1.0D) and redbear-ci.yml, with a unit test (test-patch-sanity.sh). Skips archived/legacy trees and unvalidatable formats (empty placeholders, bare-@@ git hunks).
127 lines
5.3 KiB
C++
127 lines
5.3 KiB
C++
// RUN: %clang_cc1 -std=c++11 -triple x86_64-apple-darwin %s -emit-llvm -o - | FileCheck -check-prefixes=X64,CHECK %s
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// RUN: %clang_cc1 -std=c++11 -triple amdgcn %s -emit-llvm -o - | FileCheck -check-prefixes=AMDGCN,CHECK %s
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template<typename T>
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struct S {
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static int n;
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};
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template<typename T> int S<T>::n = 5;
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int f() {
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// Make sure that the reference here is enough to trigger the instantiation of
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// the static data member.
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// CHECK: @_ZN1SIiE1nE = linkonce_odr{{.*}} global i32 5
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int a[S<int>::n];
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return sizeof a;
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}
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void test0(void *array, int n) {
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// CHECK-LABEL: define{{.*}} void @_Z5test0Pvi(
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// AMDGCN: [[ARRAY0:%.*]] = alloca ptr, align 8, addrspace(5)
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// AMDGCN-NEXT: [[N0:%.*]] = alloca i32, align 4, addrspace(5)
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// AMDGCN-NEXT: [[REF0:%.*]] = alloca ptr, align 8, addrspace(5)
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// AMDGCN-NEXT: [[S0:%.*]] = alloca i16, align 2, addrspace(5)
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// AMDGCN-NEXT: [[ARRAY:%.*]] = addrspacecast ptr addrspace(5) [[ARRAY0]] to ptr
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// AMDGCN-NEXT: [[N:%.*]] = addrspacecast ptr addrspace(5) [[N0]] to ptr
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// AMDGCN-NEXT: [[REF:%.*]] = addrspacecast ptr addrspace(5) [[REF0]] to ptr
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// AMDGCN-NEXT: [[S:%.*]] = addrspacecast ptr addrspace(5) [[S0]] to ptr
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// X64: [[ARRAY:%.*]] = alloca ptr, align 8
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// X64-NEXT: [[N:%.*]] = alloca i32, align 4
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// X64-NEXT: [[REF:%.*]] = alloca ptr, align 8
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// X64-NEXT: [[S:%.*]] = alloca i16, align 2
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// CHECK-NEXT: store ptr
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// CHECK-NEXT: store i32
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// Capture the bounds.
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// CHECK-NEXT: [[T0:%.*]] = load i32, ptr [[N]], align 4
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// CHECK-NEXT: [[DIM0:%.*]] = zext i32 [[T0]] to i64
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// CHECK-NEXT: [[T0:%.*]] = load i32, ptr [[N]], align 4
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// CHECK-NEXT: [[T1:%.*]] = add nsw i32 [[T0]], 1
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// CHECK-NEXT: [[DIM1:%.*]] = zext i32 [[T1]] to i64
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typedef short array_t[n][n+1];
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// CHECK-NEXT: [[T0:%.*]] = load ptr, ptr [[ARRAY]], align 8
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// CHECK-NEXT: store ptr [[T0]], ptr [[REF]], align 8
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array_t &ref = *(array_t*) array;
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// CHECK-NEXT: [[T0:%.*]] = load ptr, ptr [[REF]]
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// CHECK-NEXT: [[T1:%.*]] = mul nsw i64 1, [[DIM1]]
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// CHECK-NEXT: [[T2:%.*]] = getelementptr inbounds i16, ptr [[T0]], i64 [[T1]]
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// CHECK-NEXT: [[T3:%.*]] = getelementptr inbounds i16, ptr [[T2]], i64 2
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// CHECK-NEXT: store i16 3, ptr [[T3]]
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ref[1][2] = 3;
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// CHECK-NEXT: [[T0:%.*]] = load ptr, ptr [[REF]]
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// CHECK-NEXT: [[T1:%.*]] = mul nsw i64 4, [[DIM1]]
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// CHECK-NEXT: [[T2:%.*]] = getelementptr inbounds i16, ptr [[T0]], i64 [[T1]]
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// CHECK-NEXT: [[T3:%.*]] = getelementptr inbounds i16, ptr [[T2]], i64 5
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// CHECK-NEXT: [[T4:%.*]] = load i16, ptr [[T3]]
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// CHECK-NEXT: store i16 [[T4]], ptr [[S]], align 2
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short s = ref[4][5];
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// CHECK-NEXT: ret void
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}
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void test2(int b) {
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// CHECK-LABEL: define{{.*}} void {{.*}}test2{{.*}}(i32 noundef %b)
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int varr[b];
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// AMDGCN: %__end1 = alloca ptr, align 8, addrspace(5)
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// AMDGCN: [[END:%.*]] = addrspacecast ptr addrspace(5) %__end1 to ptr
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// get the address of %b by checking the first store that stores it
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//CHECK: store i32 %b, ptr [[PTR_B:%.*]]
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// get the size of the VLA by getting the first load of the PTR_B
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//CHECK: [[VLA_NUM_ELEMENTS_PREZEXT:%.*]] = load i32, ptr [[PTR_B]]
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//CHECK-NEXT: [[VLA_NUM_ELEMENTS_PRE:%.*]] = zext i32 [[VLA_NUM_ELEMENTS_PREZEXT]]
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b = 15;
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//CHECK: store i32 15, ptr [[PTR_B]]
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// Now get the sizeof, and then divide by the element size
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//CHECK: [[VLA_SIZEOF:%.*]] = mul nuw i64 4, [[VLA_NUM_ELEMENTS_PRE]]
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//CHECK-NEXT: [[VLA_NUM_ELEMENTS_POST:%.*]] = udiv i64 [[VLA_SIZEOF]], 4
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//CHECK-NEXT: [[VLA_END_PTR:%.*]] = getelementptr inbounds nuw i32, ptr {{%.*}}, i64 [[VLA_NUM_ELEMENTS_POST]]
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//X64-NEXT: store ptr [[VLA_END_PTR]], ptr %__end1
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//AMDGCN-NEXT: store ptr [[VLA_END_PTR]], ptr [[END]]
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for (int d : varr) 0;
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}
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void test3(int b, int c) {
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// CHECK-LABEL: define{{.*}} void {{.*}}test3{{.*}}(i32 noundef %b, i32 noundef %c)
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int varr[b][c];
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// AMDGCN: %__end1 = alloca ptr, align 8, addrspace(5)
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// AMDGCN: [[END:%.*]] = addrspacecast ptr addrspace(5) %__end1 to ptr
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// get the address of %b by checking the first store that stores it
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//CHECK: store i32 %b, ptr [[PTR_B:%.*]]
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//CHECK-NEXT: store i32 %c, ptr [[PTR_C:%.*]]
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// get the size of the VLA by getting the first load of the PTR_B
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//CHECK: [[VLA_DIM1_PREZEXT:%.*]] = load i32, ptr [[PTR_B]]
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//CHECK-NEXT: [[VLA_DIM1_PRE:%.*]] = zext i32 [[VLA_DIM1_PREZEXT]]
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//CHECK: [[VLA_DIM2_PREZEXT:%.*]] = load i32, ptr [[PTR_C]]
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//CHECK-NEXT: [[VLA_DIM2_PRE:%.*]] = zext i32 [[VLA_DIM2_PREZEXT]]
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b = 15;
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c = 15;
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//CHECK: store i32 15, ptr [[PTR_B]]
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//CHECK: store i32 15, ptr [[PTR_C]]
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// Now get the sizeof, and then divide by the element size
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// multiply the two dimensions, then by the element type and then divide by the sizeof dim2
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//CHECK: [[VLA_DIM1_X_DIM2:%.*]] = mul nuw i64 [[VLA_DIM1_PRE]], [[VLA_DIM2_PRE]]
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//CHECK-NEXT: [[VLA_SIZEOF:%.*]] = mul nuw i64 4, [[VLA_DIM1_X_DIM2]]
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//CHECK-NEXT: [[VLA_SIZEOF_DIM2:%.*]] = mul nuw i64 4, [[VLA_DIM2_PRE]]
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//CHECK-NEXT: [[VLA_NUM_ELEMENTS:%.*]] = udiv i64 [[VLA_SIZEOF]], [[VLA_SIZEOF_DIM2]]
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//CHECK-NEXT: [[VLA_END_INDEX:%.*]] = mul nsw i64 [[VLA_NUM_ELEMENTS]], [[VLA_DIM2_PRE]]
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//CHECK-NEXT: [[VLA_END_PTR:%.*]] = getelementptr inbounds nuw i32, ptr {{%.*}}, i64 [[VLA_END_INDEX]]
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//X64-NEXT: store ptr [[VLA_END_PTR]], ptr %__end
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//AMDGCN-NEXT: store ptr [[VLA_END_PTR]], ptr [[END]]
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for (auto &d : varr) 0;
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}
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