vasilito
cb424d7448
verify-patch-sanity.py validates every active recipe .patch has internally- consistent hunk line counts — catching the 'malformed patch at line N' failure at commit/CI/preflight time instead of hours into a cook. This cycle hit that class three times (qtwaylandscanner, sddm, xwayland), each only discovered when cookbook tried to apply the patch. Running it across the repo found 29 latent malformed patches (validated against GNU patch: e.g. relibc/P3-sysv-ipc reproduces 'malformed patch at line 22'). They were harmless only because they sit in vendored recipes (baked, not re- applied) — but would fail on any version-bump re-derivation. --fix recounts the hunk headers (body untouched) and repaired all 29. Wired into build-preflight.sh (Phase 1.0D) and redbear-ci.yml, with a unit test (test-patch-sanity.sh). Skips archived/legacy trees and unvalidatable formats (empty placeholders, bare-@@ git hunks).
127 lines
6.8 KiB
C
127 lines
6.8 KiB
C
// RUN: %clang_cc1 -triple arm-linux-gnueabi -emit-llvm %s -o - | FileCheck %s -check-prefix=ARM
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// RUN: %clang_cc1 -triple powerpc-linux-gnu -emit-llvm %s -o - | FileCheck %s -check-prefix=PPC32
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// RUN: %clang_cc1 -triple powerpc64-linux-gnu -emit-llvm %s -o - | FileCheck %s -check-prefix=PPC64
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// RUN: %clang_cc1 -triple mipsel-linux-gnu -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS32
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// RUN: %clang_cc1 -triple mipsisa32r6el-linux-gnu -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS32
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// RUN: %clang_cc1 -triple mips64el-linux-gnu -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS64
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// RUN: %clang_cc1 -triple mips64el-linux-gnuabi64 -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS64
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// RUN: %clang_cc1 -triple mipsisa64r6el-linux-gnuabi64 -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS64
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// RUN: %clang_cc1 -triple sparc-unknown-eabi -emit-llvm %s -o - | FileCheck %s -check-prefix=SPARCV8 -check-prefix=SPARC
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// RUN: %clang_cc1 -triple sparcv9-unknown-eabi -emit-llvm %s -o - | FileCheck %s -check-prefix=SPARCV9 -check-prefix=SPARC
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// RUN: %clang_cc1 -triple nvptx64-nvidia-cuda -emit-llvm %s -o - | FileCheck %s -check-prefix=NVPTX
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unsigned char c1, c2;
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unsigned short s1, s2;
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unsigned int i1, i2;
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unsigned long long ll1, ll2;
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unsigned char a1[100], a2[100];
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enum memory_order {
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memory_order_relaxed,
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memory_order_consume,
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memory_order_acquire,
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memory_order_release,
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memory_order_acq_rel,
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memory_order_seq_cst
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};
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void test1(void) {
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(void)__atomic_load(&c1, &c2, memory_order_seq_cst);
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(void)__atomic_store(&c1, &c2, memory_order_seq_cst);
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(void)__atomic_load(&s1, &s2, memory_order_seq_cst);
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(void)__atomic_store(&s1, &s2, memory_order_seq_cst);
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(void)__atomic_load(&i1, &i2, memory_order_seq_cst);
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(void)__atomic_store(&i1, &i2, memory_order_seq_cst);
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(void)__atomic_load(&ll1, &ll2, memory_order_seq_cst);
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(void)__atomic_store(&ll1, &ll2, memory_order_seq_cst);
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(void)__atomic_load(&a1, &a2, memory_order_seq_cst);
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(void)__atomic_store(&a1, &a2, memory_order_seq_cst);
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// ARM-LABEL: define{{.*}} void @test1
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// ARM: = load atomic i8, ptr @c1 seq_cst, align 1
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// ARM: store atomic i8 {{.*}}, ptr @c1 seq_cst, align 1
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// ARM: = load atomic i16, ptr @s1 seq_cst, align 2
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// ARM: store atomic i16 {{.*}}, ptr @s1 seq_cst, align 2
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// ARM: = load atomic i32, ptr @i1 seq_cst, align 4
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// ARM: store atomic i32 {{.*}}, ptr @i1 seq_cst, align 4
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// ARM: = load atomic i64, ptr @ll1 seq_cst, align 8
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// ARM: store atomic i64 {{.*}}, ptr @ll1 seq_cst, align 8
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// ARM: call{{.*}} void @__atomic_load(i32 noundef 100, ptr noundef @a1, ptr noundef @a2
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// ARM: call{{.*}} void @__atomic_store(i32 noundef 100, ptr noundef @a1, ptr noundef @a2
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// PPC32-LABEL: define{{.*}} void @test1
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// PPC32: = load atomic i8, ptr @c1 seq_cst, align 1
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// PPC32: store atomic i8 {{.*}}, ptr @c1 seq_cst, align 1
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// PPC32: = load atomic i16, ptr @s1 seq_cst, align 2
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// PPC32: store atomic i16 {{.*}}, ptr @s1 seq_cst, align 2
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// PPC32: = load atomic i32, ptr @i1 seq_cst, align 4
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// PPC32: store atomic i32 {{.*}}, ptr @i1 seq_cst, align 4
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// PPC32: = load atomic i64, ptr @ll1 seq_cst, align 8
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// PPC32: store atomic i64 {{.*}}, ptr @ll1 seq_cst, align 8
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// PPC32: call void @__atomic_load(i32 noundef 100, ptr noundef @a1, ptr noundef @a2
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// PPC32: call void @__atomic_store(i32 noundef 100, ptr noundef @a1, ptr noundef @a2
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// PPC64-LABEL: define{{.*}} void @test1
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// PPC64: = load atomic i8, ptr @c1 seq_cst, align 1
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// PPC64: store atomic i8 {{.*}}, ptr @c1 seq_cst, align 1
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// PPC64: = load atomic i16, ptr @s1 seq_cst, align 2
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// PPC64: store atomic i16 {{.*}}, ptr @s1 seq_cst, align 2
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// PPC64: = load atomic i32, ptr @i1 seq_cst, align 4
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// PPC64: store atomic i32 {{.*}}, ptr @i1 seq_cst, align 4
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// PPC64: = load atomic i64, ptr @ll1 seq_cst, align 8
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// PPC64: store atomic i64 {{.*}}, ptr @ll1 seq_cst, align 8
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// PPC64: call void @__atomic_load(i64 noundef 100, ptr noundef @a1, ptr noundef @a2
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// PPC64: call void @__atomic_store(i64 noundef 100, ptr noundef @a1, ptr noundef @a2
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// MIPS32-LABEL: define{{.*}} void @test1
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// MIPS32: = load atomic i8, ptr @c1 seq_cst, align 1
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// MIPS32: store atomic i8 {{.*}}, ptr @c1 seq_cst, align 1
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// MIPS32: = load atomic i16, ptr @s1 seq_cst, align 2
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// MIPS32: store atomic i16 {{.*}}, ptr @s1 seq_cst, align 2
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// MIPS32: = load atomic i32, ptr @i1 seq_cst, align 4
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// MIPS32: store atomic i32 {{.*}}, ptr @i1 seq_cst, align 4
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// MIPS32: = load atomic i64, ptr @ll1 seq_cst, align 8
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// MIPS32: store atomic i64 {{.*}}, ptr @ll1 seq_cst, align 8
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// MIPS32: call void @__atomic_load(i32 noundef signext 100, ptr noundef @a1, ptr noundef @a2
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// MIPS32: call void @__atomic_store(i32 noundef signext 100, ptr noundef @a1, ptr noundef @a2
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// MIPS64-LABEL: define{{.*}} void @test1
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// MIPS64: = load atomic i8, ptr @c1 seq_cst, align 1
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// MIPS64: store atomic i8 {{.*}}, ptr @c1 seq_cst, align 1
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// MIPS64: = load atomic i16, ptr @s1 seq_cst, align 2
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// MIPS64: store atomic i16 {{.*}}, ptr @s1 seq_cst, align 2
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// MIPS64: = load atomic i32, ptr @i1 seq_cst, align 4
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// MIPS64: store atomic i32 {{.*}}, ptr @i1 seq_cst, align 4
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// MIPS64: = load atomic i64, ptr @ll1 seq_cst, align 8
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// MIPS64: store atomic i64 {{.*}}, ptr @ll1 seq_cst, align 8
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// MIPS64: call void @__atomic_load(i64 noundef zeroext 100, ptr noundef @a1, ptr noundef @a2
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// MIPS64: call void @__atomic_store(i64 noundef zeroext 100, ptr noundef @a1, ptr noundef @a2
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// SPARC-LABEL: define{{.*}} void @test1
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// SPARC: = load atomic i8, ptr @c1 seq_cst, align 1
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// SPARC: store atomic i8 {{.*}}, ptr @c1 seq_cst, align 1
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// SPARC: = load atomic i16, ptr @s1 seq_cst, align 2
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// SPARC: store atomic i16 {{.*}}, ptr @s1 seq_cst, align 2
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// SPARC: = load atomic i32, ptr @i1 seq_cst, align 4
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// SPARC: store atomic i32 {{.*}}, ptr @i1 seq_cst, align 4
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// SPARC: load atomic i64, ptr @ll1 seq_cst, align 8
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// SPARC: store atomic i64 {{.*}}, ptr @ll1 seq_cst, align 8
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// SPARCV8: call void @__atomic_load(i32 noundef 100, ptr noundef @a1, ptr noundef @a2
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// SPARCV8: call void @__atomic_store(i32 noundef 100, ptr noundef @a1, ptr noundef @a2
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// SPARCV9: call void @__atomic_load(i64 noundef 100, ptr noundef @a1, ptr noundef @a2
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// SPARCV9: call void @__atomic_store(i64 noundef 100, ptr noundef @a1, ptr noundef @a2
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// NVPTX-LABEL: define{{.*}} void @test1
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// NVPTX: = load atomic i8, ptr @c1 seq_cst, align 1
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// NVPTX: store atomic i8 {{.*}}, ptr @c1 seq_cst, align 1
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// NVPTX: = load atomic i16, ptr @s1 seq_cst, align 2
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// NVPTX: store atomic i16 {{.*}}, ptr @s1 seq_cst, align 2
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// NVPTX: = load atomic i32, ptr @i1 seq_cst, align 4
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// NVPTX: store atomic i32 {{.*}}, ptr @i1 seq_cst, align 4
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// NVPTX: = load atomic i64, ptr @ll1 seq_cst, align 8
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// NVPTX: store atomic i64 {{.*}}, ptr @ll1 seq_cst, align 8
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// NVPTX: call void @__atomic_load(i64 noundef 100, ptr noundef @a1, ptr noundef @a2
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// NVPTX: call void @__atomic_store(i64 noundef 100, ptr noundef @a1, ptr noundef @a2
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}
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