vasilito
b9874d0941
Add redbear-usb-storage-check in-guest binary that validates USB mass storage read and write I/O: discovers /scheme/disk/ devices, writes a test pattern to sector 2048, reads it back, verifies match, restores original content. Updates test-usb-storage-qemu.sh with write-proof verification step. Includes all accumulated Red Bear OS work: kernel patches, relibc patches, driver infrastructure, DRM/GPU, KDE recipes, firmware, validation tooling, build system hardening, and documentation.
316 lines
10 KiB
Rust
316 lines
10 KiB
Rust
#![allow(non_snake_case)]
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#![allow(non_camel_case_types)]
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#![allow(non_upper_case_globals)]
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#![allow(clippy::unreadable_literal)]
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pub const IXGBE_EIMC: u32 = 0x00888;
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pub const IXGBE_CTRL: u32 = 0x00000;
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pub const IXGBE_CTRL_LNK_RST: u32 = 0x00000008; /* Link Reset. Resets everything. */
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pub const IXGBE_CTRL_RST: u32 = 0x04000000; /* Reset (SW) */
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pub const IXGBE_CTRL_RST_MASK: u32 = IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST;
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pub const IXGBE_EEC: u32 = 0x10010;
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pub const IXGBE_EEC_ARD: u32 = 0x00000200; /* EEPROM Auto Read Done */
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pub const IXGBE_RDRXCTL: u32 = 0x02F00;
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pub const IXGBE_RDRXCTL_RESERVED_BITS: u32 = 1 << 25 | 1 << 26;
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pub const IXGBE_RDRXCTL_DMAIDONE: u32 = 0x00000008; /* DMA init cycle done */
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pub const IXGBE_AUTOC: u32 = 0x042A0;
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pub const IXGBE_AUTOC_LMS_SHIFT: u32 = 13;
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pub const IXGBE_AUTOC_LMS_MASK: u32 = 0x7 << IXGBE_AUTOC_LMS_SHIFT;
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pub const IXGBE_AUTOC_LMS_10G_SERIAL: u32 = 0x3 << IXGBE_AUTOC_LMS_SHIFT;
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pub const IXGBE_AUTOC_10G_PMA_PMD_MASK: u32 = 0x00000180;
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pub const IXGBE_AUTOC_10G_PMA_PMD_SHIFT: u32 = 7;
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pub const IXGBE_AUTOC_10G_XAUI: u32 = 0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT;
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pub const IXGBE_AUTOC_AN_RESTART: u32 = 0x00001000;
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pub const IXGBE_GPRC: u32 = 0x04074;
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pub const IXGBE_GPTC: u32 = 0x04080;
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pub const IXGBE_GORCL: u32 = 0x04088;
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pub const IXGBE_GORCH: u32 = 0x0408C;
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pub const IXGBE_GOTCL: u32 = 0x04090;
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pub const IXGBE_GOTCH: u32 = 0x04094;
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pub const IXGBE_RXCTRL: u32 = 0x03000;
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pub const IXGBE_RXCTRL_RXEN: u32 = 0x00000001; /* Enable Receiver */
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pub fn IXGBE_RXPBSIZE(i: u32) -> u32 {
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0x03C00 + (i * 4)
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}
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pub const IXGBE_RXPBSIZE_128KB: u32 = 0x00020000; /* 128KB Packet Buffer */
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pub const IXGBE_HLREG0: u32 = 0x04240;
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pub const IXGBE_HLREG0_RXCRCSTRP: u32 = 0x00000002; /* bit 1 */
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pub const IXGBE_RDRXCTL_CRCSTRIP: u32 = 0x00000002; /* CRC Strip */
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pub const IXGBE_FCTRL: u32 = 0x05080;
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pub const IXGBE_FCTRL_BAM: u32 = 0x00000400; /* Broadcast Accept Mode */
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pub fn IXGBE_SRRCTL(i: u32) -> u32 {
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if i <= 15 {
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0x02100 + (i * 4)
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} else if i < 64 {
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0x01014 + (i * 0x40)
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} else {
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0x0D014 + ((i - 64) * 0x40)
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}
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}
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pub const IXGBE_SRRCTL_DESCTYPE_MASK: u32 = 0x0E000000;
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pub const IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF: u32 = 0x02000000;
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pub const IXGBE_SRRCTL_DROP_EN: u32 = 0x10000000;
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pub fn IXGBE_RDBAL(i: u32) -> u32 {
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if i < 64 {
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0x01000 + (i * 0x40)
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} else {
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0x0D000 + ((i - 64) * 0x40)
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}
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}
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pub fn IXGBE_RDBAH(i: u32) -> u32 {
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if i < 64 {
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0x01004 + (i * 0x40)
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} else {
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0x0D004 + ((i - 64) * 0x40)
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}
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}
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pub fn IXGBE_RDLEN(i: u32) -> u32 {
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if i < 64 {
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0x01008 + (i * 0x40)
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} else {
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0x0D008 + ((i - 64) * 0x40)
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}
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}
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pub fn IXGBE_RDH(i: u32) -> u32 {
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if i < 64 {
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0x01010 + (i * 0x40)
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} else {
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0x0D010 + ((i - 64) * 0x40)
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}
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}
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pub fn IXGBE_RDT(i: u32) -> u32 {
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if i < 64 {
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0x01018 + (i * 0x40)
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} else {
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0x0D018 + ((i - 64) * 0x40)
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}
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}
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pub const IXGBE_CTRL_EXT: u32 = 0x00018;
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pub const IXGBE_CTRL_EXT_NS_DIS: u32 = 0x00010000; /* No Snoop disable */
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pub fn IXGBE_DCA_RXCTRL(i: u32) -> u32 {
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if i <= 15 {
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0x02200 + (i * 4)
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} else if i < 64 {
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0x0100C + (i * 0x40)
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} else {
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0x0D00C + ((i - 64) * 0x40)
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}
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}
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pub const IXGBE_HLREG0_TXCRCEN: u32 = 0x00000001; /* bit 0 */
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pub const IXGBE_HLREG0_TXPADEN: u32 = 0x00000400; /* bit 10 */
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pub fn IXGBE_TXPBSIZE(i: u32) -> u32 {
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0x0CC00 + (i * 4)
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} /* 8 of these */
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pub const IXGBE_TXPBSIZE_40KB: u32 = 0x0000A000; /* 40KB Packet Buffer */
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pub const IXGBE_DTXMXSZRQ: u32 = 0x08100;
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pub const IXGBE_RTTDCS: u32 = 0x04900;
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pub const IXGBE_RTTDCS_ARBDIS: u32 = 0x00000040; /* DCB arbiter disable */
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pub fn IXGBE_TDBAL(i: u32) -> u32 {
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0x06000 + (i * 0x40)
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} /* 32 of them (0-31)*/
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pub fn IXGBE_TDBAH(i: u32) -> u32 {
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0x06004 + (i * 0x40)
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}
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pub fn IXGBE_TDLEN(i: u32) -> u32 {
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0x06008 + (i * 0x40)
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}
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pub fn IXGBE_TXDCTL(i: u32) -> u32 {
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0x06028 + (i * 0x40)
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}
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pub const IXGBE_DMATXCTL: u32 = 0x04A80;
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pub const IXGBE_DMATXCTL_TE: u32 = 0x1; /* Transmit Enable */
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pub fn IXGBE_RXDCTL(i: u32) -> u32 {
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if i < 64 {
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0x01028 + (i * 0x40)
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} else {
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0x0D028 + ((i - 64) * 0x40)
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}
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}
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pub const IXGBE_RXDCTL_ENABLE: u32 = 0x02000000; /* Ena specific Rx Queue */
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pub const IXGBE_TXDCTL_ENABLE: u32 = 0x02000000; /* Ena specific Tx Queue */
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pub fn IXGBE_TDH(i: u32) -> u32 {
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0x06010 + (i * 0x40)
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}
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pub fn IXGBE_TDT(i: u32) -> u32 {
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0x06018 + (i * 0x40)
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}
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pub const IXGBE_FCTRL_MPE: u32 = 0x00000100; /* Multicast Promiscuous Ena*/
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pub const IXGBE_FCTRL_UPE: u32 = 0x00000200; /* Unicast Promiscuous Ena */
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pub const IXGBE_LINKS: u32 = 0x042A4;
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pub const IXGBE_LINKS_UP: u32 = 0x40000000;
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pub const IXGBE_LINKS_SPEED_82599: u32 = 0x30000000;
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pub const IXGBE_LINKS_SPEED_100_82599: u32 = 0x10000000;
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pub const IXGBE_LINKS_SPEED_1G_82599: u32 = 0x20000000;
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pub const IXGBE_LINKS_SPEED_10G_82599: u32 = 0x30000000;
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pub fn IXGBE_RAL(i: u32) -> u32 {
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if i <= 15 {
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0x05400 + (i * 8)
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} else {
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0x0A200 + (i * 8)
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}
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}
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pub fn IXGBE_RAH(i: u32) -> u32 {
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if i <= 15 {
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0x05404 + (i * 8)
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} else {
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0x0A204 + (i * 8)
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}
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}
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pub const IXGBE_RXD_STAT_DD: u32 = 0x01; /* Descriptor Done */
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pub const IXGBE_RXD_STAT_EOP: u32 = 0x02; /* End of Packet */
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pub const IXGBE_RXDADV_STAT_DD: u32 = IXGBE_RXD_STAT_DD; /* Done */
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pub const IXGBE_RXDADV_STAT_EOP: u32 = IXGBE_RXD_STAT_EOP; /* End of Packet */
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pub const IXGBE_ADVTXD_PAYLEN_SHIFT: u32 = 14; /* Adv desc PAYLEN shift */
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pub const IXGBE_TXD_CMD_EOP: u32 = 0x01000000; /* End of Packet */
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pub const IXGBE_ADVTXD_DCMD_EOP: u32 = IXGBE_TXD_CMD_EOP; /* End of Packet */
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pub const IXGBE_TXD_CMD_RS: u32 = 0x08000000; /* Report Status */
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pub const IXGBE_ADVTXD_DCMD_RS: u32 = IXGBE_TXD_CMD_RS; /* Report Status */
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pub const IXGBE_TXD_CMD_IFCS: u32 = 0x02000000; /* Insert FCS (Ethernet CRC) */
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pub const IXGBE_ADVTXD_DCMD_IFCS: u32 = IXGBE_TXD_CMD_IFCS; /* Insert FCS */
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pub const IXGBE_TXD_CMD_DEXT: u32 = 0x20000000; /* Desc extension (0 = legacy) */
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pub const IXGBE_ADVTXD_DTYP_DATA: u32 = 0x00300000; /* Adv Data Descriptor */
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pub const IXGBE_ADVTXD_DCMD_DEXT: u32 = IXGBE_TXD_CMD_DEXT; /* Desc ext 1=Adv */
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pub const IXGBE_TXD_STAT_DD: u32 = 0x00000001; /* Descriptor Done */
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pub const IXGBE_ADVTXD_STAT_DD: u32 = IXGBE_TXD_STAT_DD; /* Descriptor Done */
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/* Interrupt Registers */
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pub const IXGBE_EICR: u32 = 0x00800;
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pub const IXGBE_EIAC: u32 = 0x00810;
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pub const IXGBE_EIMS: u32 = 0x00880;
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pub const IXGBE_IVAR_ALLOC_VAL: u32 = 0x80; /* Interrupt Allocation valid */
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pub const IXGBE_EICR_RTX_QUEUE: u32 = 0x0000FFFF; /* RTx Queue Interrupt */
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pub fn IXGBE_IVAR(i: u32) -> u32 {
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0x00900 + (i * 4)
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} /* 24 at 0x900-0x960 */
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#[derive(Debug, Copy, Clone)]
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#[repr(C, packed)]
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pub struct ixgbe_adv_rx_desc_read {
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pub pkt_addr: u64,
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/* Packet buffer address */
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pub hdr_addr: u64,
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/* Header buffer address */
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}
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/* Receive Descriptor - Advanced */
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#[derive(Debug, Copy, Clone)]
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#[repr(C, packed)]
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pub struct ixgbe_adv_rx_desc_wb_lower_lo_dword_hs_rss {
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pub pkt_info: u16,
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/* RSS, Pkt type */
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pub hdr_info: u16,
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/* Splithdr, hdrlen */
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}
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#[derive(Copy, Clone)]
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#[repr(C, packed)]
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pub union ixgbe_adv_rx_desc_wb_lower_lo_dword {
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pub data: u32,
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pub hs_rss: ixgbe_adv_rx_desc_wb_lower_lo_dword_hs_rss,
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}
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#[derive(Debug, Copy, Clone)]
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#[repr(C, packed)]
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pub struct ixgbe_adv_rx_desc_wb_lower_hi_dword_csum_ip {
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pub ip_id: u16,
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/* IP id */
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pub csum: u16,
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/* Packet Checksum */
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}
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#[derive(Copy, Clone)]
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#[repr(C, packed)]
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pub union ixgbe_adv_rx_desc_wb_lower_hi_dword {
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pub rss: u32,
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/* RSS Hash */
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pub csum_ip: ixgbe_adv_rx_desc_wb_lower_hi_dword_csum_ip,
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}
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#[derive(Copy, Clone)]
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#[repr(C, packed)]
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pub struct ixgbe_adv_rx_desc_wb_lower {
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pub lo_dword: ixgbe_adv_rx_desc_wb_lower_lo_dword,
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pub hi_dword: ixgbe_adv_rx_desc_wb_lower_hi_dword,
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}
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#[derive(Debug, Copy, Clone)]
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#[repr(C, packed)]
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pub struct ixgbe_adv_rx_desc_wb_upper {
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pub status_error: u32,
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/* ext status/error */
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pub length: u16,
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/* Packet length */
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pub vlan: u16,
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/* VLAN tag */
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}
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#[derive(Copy, Clone)]
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#[repr(C, packed)]
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pub struct ixgbe_adv_rx_desc_wb {
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pub lower: ixgbe_adv_rx_desc_wb_lower,
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pub upper: ixgbe_adv_rx_desc_wb_upper,
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}
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#[derive(Copy, Clone)]
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#[repr(C, packed)]
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pub union ixgbe_adv_rx_desc {
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pub read: ixgbe_adv_rx_desc_read,
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pub wb: ixgbe_adv_rx_desc_wb, /* writeback */
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_union_align: [u64; 2],
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}
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/* Transmit Descriptor - Advanced */
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#[derive(Debug, Copy, Clone)]
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#[repr(C, packed)]
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pub struct ixgbe_adv_tx_desc_read {
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pub buffer_addr: u64,
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/* Address of descriptor's data buf */
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pub cmd_type_len: u32,
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pub olinfo_status: u32,
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}
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#[derive(Debug, Copy, Clone)]
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#[repr(C, packed)]
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pub struct ixgbe_adv_tx_desc_wb {
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pub rsvd: u64,
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/* Reserved */
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pub nxtseq_seed: u32,
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pub status: u32,
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}
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#[derive(Copy, Clone)]
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#[repr(C, packed)]
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pub union ixgbe_adv_tx_desc {
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pub read: ixgbe_adv_tx_desc_read,
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pub wb: ixgbe_adv_tx_desc_wb,
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_union_align: [u64; 2],
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}
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