Files
RedBear-OS/local
vasilito f686cc27d5 base: bump submodule — acpid LPIT + _PRW wake + S0-idle (ACPICA port) (a12fb9fc)
Also update LG Gram plan doc: ACPICA assessment (port algorithms,
not the C library), pcid assessment (correct, no changes needed),
Phase 9.1 marked partial (LPIT + _PRW + S0-idle done; MWAIT loop
remains), status updated to reflect completed phases.
2026-07-22 12:26:38 +09:00
..