612 lines
23 KiB
Diff
612 lines
23 KiB
Diff
diff --git a/src/acpi/madt/arch/x86.rs b/src/acpi/madt/arch/x86.rs
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index 2cf77631..4203fec6 100644
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--- a/src/acpi/madt/arch/x86.rs
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+++ b/src/acpi/madt/arch/x86.rs
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@@ -34,18 +34,19 @@
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return;
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}
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- // Map trampoline
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+ // Map trampoline writable and executable (trampoline page holds both code
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+ // and AP argument data — AP writes ap_ready on the same page, so W^X is
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+ // not possible without splitting code/data across pages).
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let trampoline_frame = Frame::containing(PhysicalAddress::new(TRAMPOLINE));
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let trampoline_page = Page::containing_address(VirtualAddress::new(TRAMPOLINE));
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let (result, page_table_physaddr) = unsafe {
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- //TODO: do not have writable and executable!
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let mut mapper = KernelMapper::lock_rw();
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let result = mapper
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.map_phys(
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trampoline_page.start_address(),
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trampoline_frame.base(),
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- PageFlags::new().execute(true).write(true),
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+ PageFlags::new().write(true).execute(true),
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)
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.expect("failed to map trampoline");
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@@ -141,6 +142,108 @@
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RmmA::invalidate_all();
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}
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+ } else if let MadtEntry::LocalX2Apic(ap_x2apic) = madt_entry {
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+ if ap_x2apic.x2apic_id == me.get() {
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+ debug!(" This is my local x2APIC");
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+ } else if ap_x2apic.flags & 1 == 1 {
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+ let cpu_id = LogicalCpuId::next();
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+
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+ let stack_start = RmmA::phys_to_virt(
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+ allocate_p2frame(4)
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+ .expect("no more frames in acpi stack_start")
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+ .base(),
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+ )
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+ .data();
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+ let stack_end = stack_start + (PAGE_SIZE << 4);
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+
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+ let pcr_ptr = crate::arch::gdt::allocate_and_init_pcr(cpu_id, stack_end);
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+ let idt_ptr = crate::arch::idt::allocate_and_init_idt(cpu_id);
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+
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+ let args = KernelArgsAp {
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+ stack_end: stack_end as *mut u8,
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+ cpu_id,
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+ pcr_ptr,
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+ idt_ptr,
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+ };
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+
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+ let ap_ready = (TRAMPOLINE + 8) as *mut u64;
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+ let ap_args_ptr = unsafe { ap_ready.add(1) };
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+ let ap_page_table = unsafe { ap_ready.add(2) };
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+ let ap_code = unsafe { ap_ready.add(3) };
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+
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+ unsafe {
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+ ap_ready.write(0);
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+ ap_args_ptr.write(&args as *const _ as u64);
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+ ap_page_table.write(page_table_physaddr as u64);
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+ #[expect(clippy::fn_to_numeric_cast)]
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+ ap_code.write(kstart_ap as u64);
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+ core::arch::asm!("");
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+ };
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+ AP_READY.store(false, Ordering::SeqCst);
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+
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+ // Same ICR delivery-mode bits are used by xAPIC and x2APIC; only the
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+ // destination field encoding changes between the MMIO and MSR forms.
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+ const ICR_INIT_ASSERT: u64 = 0x4500;
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+ const ICR_STARTUP: u64 = 0x4600;
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+
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+ // ICR bits 10:8 = 0b101 (INIT), bit 14 = level assert.
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+ // Send INIT IPI (x2APIC always uses 32-bit APIC ID in bits 32-63)
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+ {
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+ let mut icr = ICR_INIT_ASSERT;
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+ icr |= u64::from(ap_x2apic.x2apic_id) << 32;
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+ local_apic.set_icr(icr);
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+ }
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+
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+ // Wait for INIT delivery (~10 μs de-assert window per Intel SDM)
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+ for _ in 0..100_000 {
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+ hint::spin_loop();
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+ }
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+
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+ // ICR bits 10:8 = 0b110 (STARTUP), bit 14 = level assert.
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+ // Send STARTUP IPI
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+ {
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+ let ap_segment = (TRAMPOLINE >> 12) & 0xFF;
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+ let mut icr = ICR_STARTUP | ap_segment as u64;
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+ icr |= u64::from(ap_x2apic.x2apic_id) << 32;
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+ local_apic.set_icr(icr);
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+ }
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+
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+ // Wait ~200 μs, then send second STARTUP IPI per the universal
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+ // startup algorithm.
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+ for _ in 0..2_000_000 {
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+ hint::spin_loop();
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+ }
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+ {
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+ let ap_segment = (TRAMPOLINE >> 12) & 0xFF;
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+ let mut icr = ICR_STARTUP | ap_segment as u64;
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+ icr |= u64::from(ap_x2apic.x2apic_id) << 32;
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+ local_apic.set_icr(icr);
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+ }
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+
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+ // Known limitation: cpu_id and per-CPU bootstrap state are allocated
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+ // before the timeout checks, so a timed-out AP still consumes a
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+ // logical CPU slot until startup rollback/teardown is implemented.
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+ let mut timeout = 100_000_000u32;
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+ while unsafe { (*ap_ready.cast::<AtomicU8>()).load(Ordering::SeqCst) } == 0 {
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+ hint::spin_loop();
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+ timeout -= 1;
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+ if timeout == 0 {
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+ debug!("x2APIC AP {} trampoline startup timed out", ap_x2apic.x2apic_id);
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+ break;
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+ }
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+ }
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+ let mut timeout = 100_000_000u32;
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+ while !AP_READY.load(Ordering::SeqCst) {
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+ hint::spin_loop();
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+ timeout -= 1;
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+ if timeout == 0 {
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+ debug!("x2APIC AP {} kernel startup timed out", ap_x2apic.x2apic_id);
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+ break;
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+ }
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+ }
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+
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+ RmmA::invalidate_all();
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+ }
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}
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}
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diff --git a/src/acpi/madt/mod.rs b/src/acpi/madt/mod.rs
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index 3159b9c4..69f0f2d3 100644
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--- a/src/acpi/madt/mod.rs
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+++ b/src/acpi/madt/mod.rs
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@@ -146,6 +146,17 @@ pub struct MadtGicd {
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_reserved2: [u8; 3],
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}
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+/// MADT Local x2APIC (entry type 0x9)
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+/// Used by modern AMD and Intel platforms with APIC IDs >= 255.
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+#[derive(Clone, Copy, Debug)]
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+#[repr(C, packed)]
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+pub struct MadtLocalX2Apic {
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+ _reserved: u16,
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+ pub x2apic_id: u32,
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+ pub flags: u32,
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+ pub processor_uid: u32,
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+}
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+
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/// MADT Entries
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#[derive(Debug)]
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#[allow(dead_code)]
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@@ -160,6 +171,8 @@ pub enum MadtEntry {
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InvalidGicc(usize),
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Gicd(&'static MadtGicd),
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InvalidGicd(usize),
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+ LocalX2Apic(&'static MadtLocalX2Apic),
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+ InvalidLocalX2Apic(usize),
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Unknown(u8),
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}
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@@ -224,6 +237,15 @@ impl Iterator for MadtIter {
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MadtEntry::InvalidGicd(entry_len)
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}
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}
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+ 0x9 => {
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+ if entry_len == size_of::<MadtLocalX2Apic>() + 2 {
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+ MadtEntry::LocalX2Apic(unsafe {
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+ &*((self.sdt.data_address() + self.i + 2) as *const MadtLocalX2Apic)
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+ })
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+ } else {
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+ MadtEntry::InvalidLocalX2Apic(entry_len)
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+ }
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+ }
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_ => MadtEntry::Unknown(entry_type),
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};
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diff --git a/src/arch/x86_shared/cpuid.rs b/src/arch/x86_shared/cpuid.rs
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index b3683125..be7db1be 100644
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--- a/src/arch/x86_shared/cpuid.rs
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+++ b/src/arch/x86_shared/cpuid.rs
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@@ -1,11 +1,8 @@
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use raw_cpuid::{CpuId, CpuIdResult, ExtendedFeatures, FeatureInfo};
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+#[cfg(target_arch = "x86_64")]
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pub fn cpuid() -> CpuId {
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- // FIXME check for cpuid availability during early boot and error out if it doesn't exist.
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CpuId::with_cpuid_fn(|a, c| {
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- #[cfg(target_arch = "x86")]
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- let result = unsafe { core::arch::x86::__cpuid_count(a, c) };
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- #[cfg(target_arch = "x86_64")]
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let result = unsafe { core::arch::x86_64::__cpuid_count(a, c) };
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CpuIdResult {
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eax: result.eax,
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@@ -16,6 +13,19 @@ pub fn cpuid() -> CpuId {
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})
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}
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+#[cfg(target_arch = "x86")]
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+pub fn cpuid() -> CpuId {
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+ CpuId::with_cpuid_fn(|a, c| {
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+ let result = unsafe { core::arch::x86::__cpuid_count(a, c) };
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+ CpuIdResult {
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+ eax: result.eax,
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+ ebx: result.ebx,
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+ ecx: result.ecx,
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+ edx: result.edx,
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+ }
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+ })
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+}
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+
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#[cfg_attr(not(target_arch = "x86_64"), expect(dead_code))]
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pub fn feature_info() -> FeatureInfo {
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cpuid()
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diff --git a/src/context/memory.rs b/src/context/memory.rs
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--- a/src/context/memory.rs
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+++ b/src/context/memory.rs
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@@
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let new_flags = grant_flags.write(grant_flags.has_write() && allow_writable);
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- let Some(flush) = (unsafe {
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- addr_space
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- .table
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- .utable
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- .map_phys(faulting_page.start_address(), frame.base(), new_flags)
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- }) else {
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- // TODO
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- return Err(PfError::Oom);
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- };
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+ let flush = if faulting_frame_opt.is_some() {
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+ let Some((_, _, flush)) = (unsafe {
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+ addr_space
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+ .table
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+ .utable
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+ .remap_with_full(faulting_page.start_address(), |_, _| {
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+ Some((frame.base(), new_flags))
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+ })
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+ }) else {
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+ return Err(PfError::Oom);
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+ };
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+ flush
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+ } else {
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+ let Some(flush) = (unsafe {
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+ addr_space
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+ .table
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+ .utable
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+ .map_phys(faulting_page.start_address(), frame.base(), new_flags)
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+ }) else {
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+ return Err(PfError::Oom);
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+ };
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+ flush
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+ };
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diff --git a/src/context/memory.rs b/src/context/memory.rs
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index 94519448..368efb0d 100644
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--- a/src/context/memory.rs
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+++ b/src/context/memory.rs
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@@ -927,8 +927,8 @@ impl UserGrants {
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.take_while(move |(base, info)| PageSpan::new(**base, info.page_count).intersects(span))
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.map(|(base, info)| (*base, info))
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}
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- /// Return a free region with the specified size
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- // TODO: Alignment (x86_64: 4 KiB, 2 MiB, or 1 GiB).
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+ /// Return a free region with the specified size, optionally aligned to a power-of-two
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+ /// boundary (x86_64 supports 4 KiB, 2 MiB, or 1 GiB pages).
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// TODO: Support finding grant close to a requested address?
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pub fn find_free_near(
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&self,
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@@ -936,29 +936,42 @@ impl UserGrants {
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page_count: usize,
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_near: Option<Page>,
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) -> Option<PageSpan> {
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- // Get first available hole, but do reserve the page starting from zero as most compiled
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- // languages cannot handle null pointers safely even if they point to valid memory. If an
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- // application absolutely needs to map the 0th page, they will have to do so explicitly via
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- // MAP_FIXED/MAP_FIXED_NOREPLACE.
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- // TODO: Allow explicitly allocating guard pages? Perhaps using mprotect or mmap with
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- // PROT_NONE?
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+ self.find_free_near_aligned(min, page_count, _near, 0)
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+ }
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+ pub fn find_free_near_aligned(
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+ &self,
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+ min: usize,
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+ page_count: usize,
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+ _near: Option<Page>,
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+ page_alignment: usize,
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+ ) -> Option<PageSpan> {
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+ let alignment = if page_alignment == 0 {
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+ PAGE_SIZE
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+ } else {
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+ assert!(page_alignment.is_power_of_two(), "page_alignment must be a power of two");
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+ page_alignment * PAGE_SIZE
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+ };
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let (hole_start, _hole_size) = self
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.holes
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.iter()
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.skip_while(|(hole_offset, hole_size)| hole_offset.data() + **hole_size <= min)
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.find(|(hole_offset, hole_size)| {
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- let avail_size =
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- if hole_offset.data() <= min && min <= hole_offset.data() + **hole_size {
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- **hole_size - (min - hole_offset.data())
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- } else {
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- **hole_size
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- };
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+ let base = cmp::max(hole_offset.data(), min);
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+ let aligned_base = (base + alignment - 1) & !(alignment - 1);
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+ let avail_size = if aligned_base <= hole_offset.data() + **hole_size {
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+ hole_offset.data() + **hole_size - aligned_base
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+ } else {
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+ 0
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+ };
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page_count * PAGE_SIZE <= avail_size
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})?;
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- // Create new region
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+
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+ let base = cmp::max(hole_start.data(), min);
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+ let aligned_base = (base + alignment - 1) & !(alignment - 1);
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+
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Some(PageSpan::new(
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- Page::containing_address(VirtualAddress::new(cmp::max(hole_start.data(), min))),
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+ Page::containing_address(VirtualAddress::new(aligned_base)),
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page_count,
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))
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}
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diff --git a/src/acpi/madt/mod.rs b/src/acpi/madt/mod.rs
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index 69f0f2d3..abcdef12 100644
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--- a/src/acpi/madt/mod.rs
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+++ b/src/acpi/madt/mod.rs
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@@ -189,6 +189,10 @@ impl Iterator for MadtIter {
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let entry_len =
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unsafe { *(self.sdt.data_address() as *const u8).add(self.i + 1) } as usize;
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+ if entry_len < 2 {
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+ return None;
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+ }
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+
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if self.i + entry_len <= self.sdt.data_len() {
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let item = match entry_type {
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0x0 => {
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diff --git a/src/arch/x86_shared/device/local_apic.rs b/src/arch/x86_shared/device/local_apic.rs
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index e17c4eeb..bfcc9a80 100644
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--- a/src/arch/x86_shared/device/local_apic.rs
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+++ b/src/arch/x86_shared/device/local_apic.rs
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@@ -103,8 +103,8 @@ impl LocalApic {
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pub fn id(&self) -> ApicId {
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ApicId::new(if self.x2 {
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unsafe { rdmsr(IA32_X2APIC_APICID) as u32 }
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} else {
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- unsafe { self.read(0x20) }
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+ unsafe { self.read(0x20) >> 24 }
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})
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}
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@@ -127,7 +127,14 @@
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pub fn set_icr(&mut self, value: u64) {
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if self.x2 {
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unsafe {
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- wrmsr(IA32_X2APIC_ICR, value);
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+ const PENDING: u32 = 1 << 12;
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+ while (rdmsr(IA32_X2APIC_ICR) as u32) & PENDING == PENDING {
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+ core::hint::spin_loop();
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+ }
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+ wrmsr(IA32_X2APIC_ICR, value);
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+ while (rdmsr(IA32_X2APIC_ICR) as u32) & PENDING == PENDING {
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+ core::hint::spin_loop();
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+ }
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}
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} else {
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unsafe {
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diff --git a/src/acpi/sdt.rs b/src/acpi/sdt.rs
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index 83ff67da..f49b6212 100644
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--- a/src/acpi/sdt.rs
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+++ b/src/acpi/sdt.rs
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@@ -24,4 +24,15 @@
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let header_size = size_of::<Sdt>();
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total_size.saturating_sub(header_size)
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}
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+
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+ /// Validate that the sum of all bytes in this table is zero (ACPI spec requirement).
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+ /// Returns false if the length is too small or the checksum doesn't match.
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+ pub fn validate_checksum(&self) -> bool {
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+ let len = self.length as usize;
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+ if len < size_of::<Sdt>() {
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+ return false;
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+ }
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+ let bytes = unsafe { core::slice::from_raw_parts(self as *const _ as *const u8, len) };
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+ bytes.iter().fold(0u8, |sum, &b| sum.wrapping_add(b)) == 0
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+ }
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}
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diff --git a/src/acpi/mod.rs b/src/acpi/mod.rs
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index 59e35265..80a40a01 100644
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--- a/src/acpi/mod.rs
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+++ b/src/acpi/mod.rs
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@@ -137,6 +137,15 @@
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for sdt_address in rxsdt.iter() {
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let sdt = &*(RmmA::phys_to_virt(sdt_address).data() as *const Sdt);
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+
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+ if !sdt.validate_checksum() {
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+ let sig = &sdt.signature;
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+ warn!(
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+ "ACPI table {:?} at {:#x} has invalid checksum",
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+ sig,
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+ sdt_address.data()
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+ );
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+ }
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let signature = get_sdt_signature(sdt);
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if let Some(ref mut ptrs) = *(SDT_POINTERS.write()) {
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diff --git a/src/acpi/madt/mod.rs b/src/acpi/madt/mod.rs
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index abcdef12..bcdef123 100644
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--- a/src/acpi/madt/mod.rs
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+++ b/src/acpi/madt/mod.rs
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@@ -153,10 +153,45 @@ pub struct MadtLocalX2Apic {
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_reserved: u16,
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pub x2apic_id: u32,
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pub flags: u32,
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pub processor_uid: u32,
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}
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+/// MADT Local APIC NMI (entry type 0x4)
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+/// Configures NMI routing to a processor's LINT0/LINT1 pin.
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+#[derive(Clone, Copy, Debug)]
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+#[repr(C, packed)]
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+pub struct MadtLocalApicNmi {
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+ pub processor: u8, // 0xFF = all processors
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+ pub flags: u16, // bits 0-1: polarity, bits 2-3: trigger mode
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+ pub nmi_pin: u8, // 0 = LINT0, 1 = LINT1
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+}
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+
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+/// MADT Local APIC Address Override (entry type 0x5)
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|
+/// Provides 64-bit override for the 32-bit local APIC address.
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|
+#[derive(Clone, Copy, Debug)]
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|
+#[repr(C, packed)]
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|
+pub struct MadtLapicAddressOverride {
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|
+ _reserved: u16,
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+ pub local_apic_address: u64,
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|
+}
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|
+
|
|
+/// MADT Local x2APIC NMI (entry type 0xA)
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|
+/// x2APIC equivalent of type 0x4 for APIC IDs >= 255.
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|
+#[derive(Clone, Copy, Debug)]
|
|
+#[repr(C, packed)]
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|
+pub struct MadtLocalX2ApicNmi {
|
|
+ _reserved: u16,
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|
+ pub processor_uid: u32, // 0xFFFFFFFF = all processors
|
|
+ pub flags: u16,
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|
+ pub nmi_pin: u8, // 0 = LINT0, 1 = LINT1
|
|
+ _reserved2: u8,
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|
+}
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|
+
|
|
+const _: () = assert!(size_of::<MadtLocalApicNmi>() == 4);
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+const _: () = assert!(size_of::<MadtLapicAddressOverride>() == 10);
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+const _: () = assert!(size_of::<MadtLocalX2ApicNmi>() == 10);
|
|
+
|
|
/// MADT Entries
|
|
#[derive(Debug)]
|
|
#[allow(dead_code)]
|
|
pub enum MadtEntry {
|
|
@@ -172,6 +207,12 @@ pub enum MadtEntry {
|
|
Gicd(&'static MadtGicd),
|
|
InvalidGicd(usize),
|
|
LocalX2Apic(&'static MadtLocalX2Apic),
|
|
InvalidLocalX2Apic(usize),
|
|
+ LocalApicNmi(&'static MadtLocalApicNmi),
|
|
+ InvalidLocalApicNmi(usize),
|
|
+ LapicAddressOverride(&'static MadtLapicAddressOverride),
|
|
+ InvalidLapicAddressOverride(usize),
|
|
+ LocalX2ApicNmi(&'static MadtLocalX2ApicNmi),
|
|
+ InvalidLocalX2ApicNmi(usize),
|
|
Unknown(u8),
|
|
}
|
|
diff --git a/src/acpi/madt/mod.rs b/src/acpi/madt/mod.rs
|
|
index bcdef123..cdef1234 100644
|
|
--- a/src/acpi/madt/mod.rs
|
|
+++ b/src/acpi/madt/mod.rs
|
|
@@ -235,12 +235,40 @@ impl Iterator for MadtIter {
|
|
0x9 => {
|
|
if entry_len == size_of::<MadtLocalX2Apic>() + 2 {
|
|
MadtEntry::LocalX2Apic(unsafe {
|
|
&*((self.sdt.data_address() + self.i + 2) as *const MadtLocalX2Apic)
|
|
})
|
|
} else {
|
|
MadtEntry::InvalidLocalX2Apic(entry_len)
|
|
}
|
|
}
|
|
+ 0x4 => {
|
|
+ if entry_len == size_of::<MadtLocalApicNmi>() + 2 {
|
|
+ MadtEntry::LocalApicNmi(unsafe {
|
|
+ &*((self.sdt.data_address() + self.i + 2) as *const MadtLocalApicNmi)
|
|
+ })
|
|
+ } else {
|
|
+ MadtEntry::InvalidLocalApicNmi(entry_len)
|
|
+ }
|
|
+ }
|
|
+ 0x5 => {
|
|
+ if entry_len == size_of::<MadtLapicAddressOverride>() + 2 {
|
|
+ MadtEntry::LapicAddressOverride(unsafe {
|
|
+ &*((self.sdt.data_address() + self.i + 2)
|
|
+ as *const MadtLapicAddressOverride)
|
|
+ })
|
|
+ } else {
|
|
+ MadtEntry::InvalidLapicAddressOverride(entry_len)
|
|
+ }
|
|
+ }
|
|
+ 0xA => {
|
|
+ if entry_len == size_of::<MadtLocalX2ApicNmi>() + 2 {
|
|
+ MadtEntry::LocalX2ApicNmi(unsafe {
|
|
+ &*((self.sdt.data_address() + self.i + 2) as *const MadtLocalX2ApicNmi)
|
|
+ })
|
|
+ } else {
|
|
+ MadtEntry::InvalidLocalX2ApicNmi(entry_len)
|
|
+ }
|
|
+ }
|
|
_ => MadtEntry::Unknown(entry_type),
|
|
};
|
|
|
|
diff --git a/src/arch/x86_shared/device/local_apic.rs b/src/arch/x86_shared/device/local_apic.rs
|
|
index bfcc9a80..c0ffee01 100644
|
|
--- a/src/arch/x86_shared/device/local_apic.rs
|
|
+++ b/src/arch/x86_shared/device/local_apic.rs
|
|
@@ -7,9 +7,12 @@ use crate::{
|
|
arch::cpuid::cpuid,
|
|
ipi::IpiKind,
|
|
memory::{map_device_memory, PhysicalAddress},
|
|
percpu::PercpuBlock,
|
|
};
|
|
|
|
+const IA32_X2APIC_LVT_LINT0: u32 = 0x835;
|
|
+const IA32_X2APIC_LVT_LINT1: u32 = 0x836;
|
|
+
|
|
#[derive(Clone, Copy, Debug)]
|
|
pub struct ApicId(u32);
|
|
|
|
@@ -260,9 +262,31 @@ impl LocalApic {
|
|
unsafe fn setup_error_int(&mut self) {
|
|
unsafe {
|
|
let vector = 49u32;
|
|
self.set_lvt_error(vector);
|
|
}
|
|
}
|
|
+
|
|
+ /// Configure the LVT entry for NMI delivery on LINT0 or LINT1.
|
|
+ /// `nmi_pin`: 0 = LINT0, 1 = LINT1
|
|
+ /// `flags`: MADT NMI flags — bits 0-1 polarity, bits 2-3 trigger mode
|
|
+ pub unsafe fn set_lvt_nmi(&mut self, nmi_pin: u8, flags: u16) {
|
|
+ let delivery_nmi: u32 = 0b100 << 8;
|
|
+ let polarity = if flags & 0x3 == 2 { 1u32 << 13 } else { 0 };
|
|
+ let trigger = if (flags >> 2) & 0x3 == 2 { 1u32 << 15 } else { 0 };
|
|
+ let lvt = delivery_nmi | polarity | trigger;
|
|
+
|
|
+ if self.x2 {
|
|
+ let msr = if nmi_pin == 0 {
|
|
+ IA32_X2APIC_LVT_LINT0
|
|
+ } else {
|
|
+ IA32_X2APIC_LVT_LINT1
|
|
+ };
|
|
+ wrmsr(msr, lvt.into());
|
|
+ } else {
|
|
+ let offset: u32 = if nmi_pin == 0 { 0x350 } else { 0x360 };
|
|
+ self.write(offset, lvt);
|
|
+ }
|
|
+ }
|
|
}
|
|
|
|
#[repr(u8)]
|
|
diff --git a/src/acpi/madt/arch/x86.rs b/src/acpi/madt/arch/x86.rs
|
|
index 4203fec6..faceb00c 100644
|
|
--- a/src/acpi/madt/arch/x86.rs
|
|
+++ b/src/acpi/madt/arch/x86.rs
|
|
@@ -132,6 +132,31 @@ pub(super) fn init(madt: Madt) {
|
|
RmmA::invalidate_all();
|
|
}
|
|
- }
|
|
+ } else if let MadtEntry::LocalApicNmi(nmi) = madt_entry {
|
|
+ let target_id = nmi.processor;
|
|
+ if target_id == 0xFF {
|
|
+ debug!(" NMI: all processors, pin={}, flags={:#x}", nmi.nmi_pin, nmi.flags);
|
|
+ unsafe { local_apic.set_lvt_nmi(nmi.nmi_pin, nmi.flags); }
|
|
+ } else {
|
|
+ let my_apic_id = local_apic.id().get() as u8;
|
|
+ if target_id == my_apic_id {
|
|
+ debug!(" NMI: processor {}, pin={}, flags={:#x}", target_id, nmi.nmi_pin, nmi.flags);
|
|
+ unsafe { local_apic.set_lvt_nmi(nmi.nmi_pin, nmi.flags); }
|
|
+ }
|
|
+ }
|
|
+ } else if let MadtEntry::LocalX2ApicNmi(nmi) = madt_entry {
|
|
+ let target_uid = nmi.processor_uid;
|
|
+ if target_uid == 0xFFFFFFFF {
|
|
+ debug!(" x2APIC NMI: all processors, pin={}, flags={:#x}", nmi.nmi_pin, nmi.flags);
|
|
+ unsafe { local_apic.set_lvt_nmi(nmi.nmi_pin, nmi.flags); }
|
|
+ } else {
|
|
+ debug!(" x2APIC NMI: uid {}, pin={}, flags={:#x}", target_uid, nmi.nmi_pin, nmi.flags);
|
|
+ unsafe { local_apic.set_lvt_nmi(nmi.nmi_pin, nmi.flags); }
|
|
+ }
|
|
+ } else if let MadtEntry::LapicAddressOverride(addr) = madt_entry {
|
|
+ if addr.local_apic_address != 0 {
|
|
+ debug!(" LAPIC address override: {:#x}", addr.local_apic_address);
|
|
+ }
|
|
+ }
|
|
}
|
|
|
|
// Unmap trampoline
|