vasilito
56be23ce6e
Expose MSR access via /scheme/sys/msr/<cpu>/<msr> for root only. Required for cpufreqd P-state control and thermal sensor drivers.
88 lines
4.2 KiB
Diff
88 lines
4.2 KiB
Diff
diff --git a/src/scheme/sys/mod.rs b/src/scheme/sys/mod.rs
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index 8f26187a..9eb35644 100644
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--- a/src/scheme/sys/mod.rs
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+++ b/src/scheme/sys/mod.rs
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@@ -47,0 +48,5 @@ enum Handle {
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+ #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
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+ Msr {
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+ cpu: usize,
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+ msr: u32,
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+ },
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@@ -135,0 +141,22 @@ impl KernelScheme for SysScheme {
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+ } else if path.starts_with("msr/") {
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+ #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
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+ {
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+ if ctx.uid != 0 {
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+ return Err(Error::new(EPERM));
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+ }
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+ let rest = &path[4..];
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+ let mut parts = rest.split('/');
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+ let cpu_str = parts.next().ok_or(Error::new(EINVAL))?;
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+ let msr_str = parts.next().ok_or(Error::new(EINVAL))?;
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+ if parts.next().is_some() {
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+ return Err(Error::new(EINVAL));
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+ }
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+ let cpu: usize = cpu_str.parse().map_err(|_| Error::new(EINVAL))?;
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+ let msr: u32 = u32::from_str_radix(msr_str, 16).map_err(|_| Error::new(EINVAL))?;
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+ let id = HANDLES.write(token.token()).insert(Handle::Msr { cpu, msr });
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+ Ok(OpenResult::SchemeLocal(id, InternalFlags::POSITIONED))
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+ }
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+ #[cfg(not(any(target_arch = "x86", target_arch = "x86_64")))]
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+ {
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+ Err(Error::new(ENOENT))
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+ }
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@@ -162,0 +190,2 @@ impl KernelScheme for SysScheme {
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+ #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
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+ Handle::Msr { .. } => return Ok(0),
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@@ -190,0 +220,10 @@ impl KernelScheme for SysScheme {
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+ #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
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+ Handle::Msr { cpu, msr } => {
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+ const FIRST: &[u8] = b"sys:msr/";
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+ let mut bytes_read = buf.copy_common_bytes_from_slice(FIRST)?;
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+ let suffix = format!("{}/{:x}", cpu, msr);
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+ if let Some(remaining) = buf.advance(FIRST.len()) {
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+ bytes_read += remaining.copy_common_bytes_from_slice(suffix.as_bytes())?;
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+ }
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+ return Ok(bytes_read);
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+ }
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@@ -217,0 +257,9 @@ impl KernelScheme for SysScheme {
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+ #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
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+ Handle::Msr { cpu, msr } => {
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+ if *cpu != crate::cpu_id().get() as usize {
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+ return Err(Error::new(EINVAL));
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+ }
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+ let val = unsafe { x86::msr::rdmsr(*msr) };
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+ let data = format!("{:016x}\n", val).into_bytes();
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+ return buffer.copy_common_bytes_from_slice(&data[pos..]);
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+ }
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@@ -255,0 +304,12 @@ impl KernelScheme for SysScheme {
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+ #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
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+ Handle::Msr { cpu, msr } => {
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+ if *cpu != crate::cpu_id().get() as usize {
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+ return Err(Error::new(EINVAL));
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+ }
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+ let mut intermediate = [0_u8; 32];
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+ let len = buffer.copy_common_bytes_to_slice(&mut intermediate)?;
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+ let val_str = core::str::from_utf8(&intermediate[..len]).map_err(|_| Error::new(EINVAL))?;
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+ let val = u64::from_str_radix(val_str.trim(), 16).map_err(|_| Error::new(EINVAL))?;
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+ unsafe { x86::msr::wrmsr(*msr, val); }
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+ return Ok(len);
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+ }
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@@ -272 +332,2 @@ impl KernelScheme for SysScheme {
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- Handle::Resource { .. } => Err(Error::new(ENOTDIR)),
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+ Handle::Resource { .. }
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+ | Handle::Msr { .. } => Err(Error::new(ENOTDIR)),
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@@ -295,0 +357,12 @@ impl KernelScheme for SysScheme {
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+ #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
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+ Handle::Msr { .. } => {
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+ let stat = Stat {
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+ st_mode: 0o600 | MODE_FILE,
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+ st_uid: 0,
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+ st_gid: 0,
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+ st_size: 0,
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+ ..Default::default()
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+ };
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+ buf.copy_exactly(&stat)?;
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+ return Ok(());
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+ }
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