intel: Xe2/Arrow Lake support — regs_xe2.rs, device IDs, generation selection
Add Arrow Lake-P Arc Pro 130T/140T (0x7d51) and other Xe2 device IDs.
Create Xe2 register table with correct forcewake (0xa188/0xdfc),
DMC (0x80000 base), and DBUF/D2D registers.
- info.rs: add GenXe2 generation (display ver 20, gt ver 20),
4 Arrow Lake device IDs, update generation gating for Xe2
(has_combo_phy, has_dbuf_slice, has_separate_transcoder = true;
has_gmbus = false — Xe2 uses DP AUX for EDID)
- regs_xe2.rs: Xe2Regs implementing IntelRegs trait with Xe2-specific
forcewake, DMC offsets. Xe2LpdRegs struct for Xe2LPD display
registers (DE_CAP, DFSM, DBUF_CTL, D2D_LINK_CTL)
- mod.rs: dynamic register table selection based on generation
(GenXe2 → Xe2Regs, default → Gen9Regs). GMBUS controller moved
to Option — initialized only for non-Xe2 platforms.
Import IntelGeneration for generation dispatch.
Linux reference: xe_pci.c (INTEL_ARL_IDS), xe_gt_regs.h,
intel_display_regs.h (XE2LPD_* defines)
Compiled: library modules clean (pre-existing daemon errors unrelated)
vasilito
f07fd649af