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vasilito e7ed83144e intel: complete DPLL reimplementation from Linux 7.1

Ported skl_ddi_calculate_wrpll() computation engine:
- DCO central frequency table (8.4/9.0/9.6 GHz)
- 43 divider values (36 even + 7 odd)
- Deviation-minimizing search across all dividers × central freqs
- skl_wrpll_multipliers() → p0×p1×p2 decomposition
- skl_wrpll_params_populate() → dco_integer/fraction with 0x8000 precision

Per-platform PLL programming:
- SKL: CFGCR0+CFGCR1+CTL at 0x164284/0x164288/0x16428C
  with qdiv_mode, kdiv/pdiv, posting reads, lock polling
- ICL: same as SKL register set
- TGL: TGL-specific CFGCR1 at 0x164298
- MTL: DPLL_FREQ + DPLL_CTRL1 with PLL_POWER_ENABLE
- Xe2: DPLL_CTRL1/CTRL2 with power+enable+lock

162 → 250 lines of actual computation and programming logic

2026-06-02 06:42:55 +03:00

Assets/images

Red Bear OS — microkernel OS in Rust, based on Redox

2026-04-12 19:05:00 +01:00

cache

migrate: finalize source ownership — mini ISO builds and boots

2026-05-30 00:38:25 +03:00

config

Merge bootprocess branch overlay into 0.2.0

2026-05-27 06:47:23 +03:00

docs

intel: fix pre-Gen9 per-gen flags, enable Gen8 PPGTT, expand plan