4lDO2
698 lines
20 KiB
Rust
698 lines
20 KiB
Rust
use std::ptr;
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use std::collections::BTreeMap;
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use std::sync::{Mutex, RwLock};
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use std::sync::atomic::{AtomicUsize, Ordering};
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use crossbeam_channel::Sender;
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use syscall::io::{Dma, Io, Mmio};
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use syscall::error::{Error, Result, EINVAL};
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pub mod cq_reactor;
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use self::cq_reactor::{self, NotifReq};
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use pcid_interface::msi::{MsiCapability, MsixCapability, MsixTableEntry};
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use pcid_interface::PcidServerHandle;
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#[derive(Debug)]
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pub enum InterruptMethod {
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Intx,
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Msi(MsiCapability),
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MsiX(MsixCfg),
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}
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#[derive(Debug)]
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pub struct MsixCfg {
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pub cap: MsixCapability,
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pub table: &'static mut [MsixTableEntry],
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pub pba: &'static mut [Mmio<u64>],
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}
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#[derive(Clone, Copy)]
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#[repr(packed)]
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pub struct NvmeCmd {
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/// Opcode
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opcode: u8,
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/// Flags
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flags: u8,
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/// Command ID
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cid: u16,
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/// Namespace identifier
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nsid: u32,
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/// Reserved
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_rsvd: u64,
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/// Metadata pointer
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mptr: u64,
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/// Data pointer
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dptr: [u64; 2],
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/// Command dword 10
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cdw10: u32,
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/// Command dword 11
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cdw11: u32,
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/// Command dword 12
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cdw12: u32,
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/// Command dword 13
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cdw13: u32,
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/// Command dword 14
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cdw14: u32,
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/// Command dword 15
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cdw15: u32,
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}
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impl NvmeCmd {
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pub fn create_io_completion_queue(cid: u16, qid: u16, ptr: usize, size: u16) -> Self {
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Self {
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opcode: 5,
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flags: 0,
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cid,
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nsid: 0,
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_rsvd: 0,
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mptr: 0,
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dptr: [ptr as u64, 0],
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cdw10: ((size as u32) << 16) | (qid as u32),
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cdw11: 1 /* Physically Contiguous */, //TODO: IV, IEN
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cdw12: 0,
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cdw13: 0,
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cdw14: 0,
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cdw15: 0,
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}
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}
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pub fn create_io_submission_queue(cid: u16, qid: u16, ptr: usize, size: u16, cqid: u16) -> Self {
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Self {
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opcode: 1,
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flags: 0,
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cid: cid,
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nsid: 0,
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_rsvd: 0,
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mptr: 0,
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dptr: [ptr as u64, 0],
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cdw10: ((size as u32) << 16) | (qid as u32),
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cdw11: ((cqid as u32) << 16) | 1 /* Physically Contiguous */, //TODO: QPRIO
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cdw12: 0, //TODO: NVMSETID
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cdw13: 0,
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cdw14: 0,
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cdw15: 0,
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}
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}
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pub fn identify_namespace(cid: u16, ptr: usize, nsid: u32) -> Self {
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Self {
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opcode: 6,
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flags: 0,
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cid: cid,
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nsid: nsid,
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_rsvd: 0,
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mptr: 0,
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dptr: [ptr as u64, 0],
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cdw10: 0,
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cdw11: 0,
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cdw12: 0,
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cdw13: 0,
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cdw14: 0,
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cdw15: 0,
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}
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}
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pub fn identify_controller(cid: u16, ptr: usize) -> Self {
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Self {
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opcode: 6,
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flags: 0,
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cid: cid,
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nsid: 0,
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_rsvd: 0,
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mptr: 0,
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dptr: [ptr as u64, 0],
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cdw10: 1,
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cdw11: 0,
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cdw12: 0,
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cdw13: 0,
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cdw14: 0,
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cdw15: 0,
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}
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}
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pub fn identify_namespace_list(cid: u16, ptr: usize, base: u32) -> Self {
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Self {
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opcode: 6,
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flags: 0,
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cid: cid,
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nsid: base,
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_rsvd: 0,
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mptr: 0,
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dptr: [ptr as u64, 0],
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cdw10: 2,
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cdw11: 0,
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cdw12: 0,
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cdw13: 0,
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cdw14: 0,
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cdw15: 0,
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}
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}
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pub fn io_read(cid: u16, nsid: u32, lba: u64, blocks_1: u16, ptr0: u64, ptr1: u64) -> Self {
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Self {
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opcode: 2,
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flags: 1 << 6,
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cid: cid,
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nsid: nsid,
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_rsvd: 0,
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mptr: 0,
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dptr: [ptr0, ptr1],
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cdw10: lba as u32,
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cdw11: (lba >> 32) as u32,
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cdw12: blocks_1 as u32,
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cdw13: 0,
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cdw14: 0,
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cdw15: 0,
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}
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}
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pub fn io_write(cid: u16, nsid: u32, lba: u64, blocks_1: u16, ptr0: u64, ptr1: u64) -> Self {
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Self {
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opcode: 1,
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flags: 1 << 6,
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cid: cid,
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nsid: nsid,
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_rsvd: 0,
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mptr: 0,
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dptr: [ptr0, ptr1],
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cdw10: lba as u32,
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cdw11: (lba >> 32) as u32,
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cdw12: blocks_1 as u32,
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cdw13: 0,
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cdw14: 0,
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cdw15: 0,
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}
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}
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}
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#[derive(Clone, Copy, Debug)]
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#[repr(packed)]
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pub struct NvmeComp {
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command_specific: u32,
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_rsvd: u32,
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sq_head: u16,
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sq_id: u16,
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cid: u16,
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status: u16,
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}
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#[repr(packed)]
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pub struct NvmeRegs {
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/// Controller Capabilities
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cap: Mmio<u64>,
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/// Version
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vs: Mmio<u32>,
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/// Interrupt mask set
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intms: Mmio<u32>,
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/// Interrupt mask clear
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intmc: Mmio<u32>,
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/// Controller configuration
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cc: Mmio<u32>,
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/// Reserved
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_rsvd: Mmio<u32>,
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/// Controller status
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csts: Mmio<u32>,
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/// NVM subsystem reset
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nssr: Mmio<u32>,
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/// Admin queue attributes
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aqa: Mmio<u32>,
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/// Admin submission queue base address
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asq: Mmio<u64>,
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/// Admin completion queue base address
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acq: Mmio<u64>,
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/// Controller memory buffer location
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cmbloc: Mmio<u32>,
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/// Controller memory buffer size
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cmbsz: Mmio<u32>,
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}
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pub struct NvmeCmdQueue {
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data: Dma<[NvmeCmd; 64]>,
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i: usize,
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}
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impl NvmeCmdQueue {
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fn new() -> Result<Self> {
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Ok(Self {
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data: Dma::zeroed()?,
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i: 0,
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})
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}
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fn submit(&mut self, entry: NvmeCmd) -> usize {
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self.data[self.i] = entry;
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self.i = (self.i + 1) % self.data.len();
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self.i
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}
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}
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pub struct NvmeCompQueue {
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data: Dma<[NvmeComp; 256]>,
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i: usize,
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phase: bool,
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}
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impl NvmeCompQueue {
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fn new() -> Result<Self> {
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Ok(Self {
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data: Dma::zeroed()?,
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i: 0,
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phase: true,
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})
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}
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pub (crate) fn complete(&mut self) -> Option<(usize, NvmeComp)> {
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let entry = unsafe {
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ptr::read_volatile(self.data.as_ptr().add(self.i))
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};
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// println!("{:?}", entry);
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if ((entry.status & 1) == 1) == self.phase {
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self.i = (self.i + 1) % self.data.len();
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if self.i == 0 {
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self.phase = ! self.phase;
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}
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Some((self.i, entry))
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} else {
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None
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}
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}
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fn complete_spin(&mut self) -> (usize, NvmeComp) {
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loop {
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if let Some(some) = self.complete() {
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return some;
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} else {
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unsafe { std::arch::x86_64::_mm_pause() }
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}
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}
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}
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}
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pub struct NvmeNamespace {
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pub id: u32,
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pub blocks: u64,
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pub block_size: u64,
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}
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pub struct Nvme {
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interrupt_method: Mutex<InterruptMethod>,
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pcid_interface: Mutex<PcidServerHandle>,
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regs: Mutex<&'static mut NvmeRegs>,
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submission_queues: RwLock<Vec<Mutex<NvmeCmdQueue>>>,
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pub (crate) completion_queues: RwLock<Vec<Mutex<NvmeCompQueue>>>,
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buffer: Mutex<Dma<[u8; 512 * 4096]>>, // 2MB of buffer
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buffer_prp: Mutex<Dma<[u64; 512]>>, // 4KB of PRP for the buffer
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reactor_sender: Sender<cq_reactor::NotifReq>,
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next_cid: AtomicUsize,
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}
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impl Nvme {
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pub fn new(address: usize, interrupt_method: InterruptMethod, pcid_interface: PcidServerHandle, reactor_sender: Sender<NotifReq>) -> Result<Self> {
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Ok(Nvme {
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regs: Mutex::new(unsafe { &mut *(address as *mut NvmeRegs) }),
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submission_queues: RwLock::new(vec! [Mutex::new(NvmeCmdQueue::new()?), Mutex::new(NvmeCmdQueue::new()?)]),
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completion_queues: RwLock::new(vec! [Mutex::new(NvmeCompQueue::new()?), Mutex::new(NvmeCompQueue::new()?)]),
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buffer: Mutex::new(Dma::zeroed()?),
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buffer_prp: Mutex::new(Dma::zeroed()?),
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next_cid: AtomicUsize::new(0),
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interrupt_method: Mutex::new(interrupt_method),
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pcid_interface: Mutex::new(pcid_interface),
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reactor_sender,
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})
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}
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unsafe fn doorbell_write(&self, index: usize, value: u32) {
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let mut regs_guard = self.regs.lock().unwrap();
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let dstrd = ((regs_guard.cap.read() >> 32) & 0b1111) as usize;
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let addr = (regs_guard as *mut u8 as usize)
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+ 0x1000
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+ index * (4 << dstrd);
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(&mut *(addr as *mut Mmio<u32>)).write(value);
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}
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pub unsafe fn submission_queue_tail(&self, qid: u16, tail: u16) {
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self.doorbell_write(2 * (qid as usize), u32::from(tail));
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}
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pub unsafe fn completion_queue_head(&self, qid: u16, head: u16) {
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self.doorbell_write(2 * (qid as usize) + 1, u32::from(head));
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}
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pub unsafe fn init(&mut self) {
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let mut buffer = self.buffer.get_mut().unwrap();
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let mut buffer_prp = self.buffer_prp.get_mut().unwrap();
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for i in 0..buffer_prp.len() {
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buffer_prp[i] = (buffer.physical() + i * 4096) as u64;
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}
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// println!(" - CAPS: {:X}", self.regs.cap.read());
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// println!(" - VS: {:X}", self.regs.vs.read());
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// println!(" - CC: {:X}", self.regs.cc.read());
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// println!(" - CSTS: {:X}", self.regs.csts.read());
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// println!(" - Disable");
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self.regs.get_mut().unwrap().cc.writef(1, false);
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// println!(" - Waiting for not ready");
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loop {
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let csts = self.regs.get_mut().unwrap().csts.read();
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// println!("CSTS: {:X}", csts);
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if csts & 1 == 1 {
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unsafe { std::arch::x86_64::_mm_pause() }
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} else {
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break;
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}
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}
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// println!(" - Mask all interrupts");
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self.regs.get_mut().unwrap().intms.write(0xFFFFFFFF); // TODO: Don't mask
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for (qid, queue) in self.completion_queues.get_mut().unwrap().iter().enumerate() {
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let data = &queue.get_mut().unwrap().data;
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// println!(" - completion queue {}: {:X}, {}", qid, data.physical(), data.len());
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}
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for (qid, queue) in self.submission_queues.get_mut().unwrap().iter().enumerate() {
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let data = &queue.get_mut().unwrap().data;
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// println!(" - submission queue {}: {:X}, {}", qid, data.physical(), data.len());
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}
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{
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let regs = self.regs.get_mut().unwrap();
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let submission_queues = self.submission_queues.get_mut().unwrap();
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let completion_queues = self.submission_queues.get_mut().unwrap();
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let asq = &submission_queues[0].get_mut().unwrap();
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let acq = &completion_queues[0].get_mut().unwrap();
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regs.aqa.write(((acq.data.len() as u32 - 1) << 16) | (asq.data.len() as u32 - 1));
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regs.asq.write(asq.data.physical() as u64);
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regs.acq.write(acq.data.physical() as u64);
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// Set IOCQES, IOSQES, AMS, MPS, and CSS
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let mut cc = regs.cc.read();
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cc &= 0xFF00000F;
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cc |= (4 << 20) | (6 << 16);
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regs.cc.write(cc);
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}
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// println!(" - Enable");
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self.regs.get_mut().unwrap().cc.writef(1, true);
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// println!(" - Waiting for ready");
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loop {
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let csts = self.regs.get_mut().unwrap().csts.read();
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// println!("CSTS: {:X}", csts);
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if csts & 1 == 0 {
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unsafe { std::arch::x86_64::_mm_pause() }
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} else {
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break;
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}
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}
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}
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pub fn init_with_queues(&self) -> BTreeMap<u32, NvmeNamespace> {
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{
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//TODO: Use buffer
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let data: Dma<[u8; 4096]> = Dma::zeroed().unwrap();
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// println!(" - Attempting to identify controller");
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{
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let qid = 0;
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let queue = &mut self.submission_queues[qid];
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let cid = queue.i as u16;
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let entry = NvmeCmd::identify_controller(
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cid, data.physical()
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);
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let tail = queue.submit(entry);
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self.submission_queue_tail(qid as u16, tail as u16);
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}
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// println!(" - Waiting to identify controller");
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{
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let qid = 0;
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let queue = &mut self.completion_queues[qid];
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let (head, entry) = queue.complete_spin();
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self.completion_queue_head(qid as u16, head as u16);
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}
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// println!(" - Dumping identify controller");
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let mut serial = String::new();
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for &b in &data[4..24] {
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if b == 0 {
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break;
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}
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serial.push(b as char);
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}
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let mut model = String::new();
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for &b in &data[24..64] {
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if b == 0 {
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break;
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}
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model.push(b as char);
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}
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let mut firmware = String::new();
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for &b in &data[64..72] {
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if b == 0 {
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break;
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}
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firmware.push(b as char);
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}
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println!(
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" - Model: {} Serial: {} Firmware: {}",
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model.trim(),
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serial.trim(),
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firmware.trim()
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);
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}
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let mut nsids = Vec::new();
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{
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//TODO: Use buffer
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let data: Dma<[u32; 1024]> = Dma::zeroed().unwrap();
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// println!(" - Attempting to retrieve namespace ID list");
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{
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let qid = 0;
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let queue = &mut self.submission_queues[qid];
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let cid = queue.i as u16;
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let entry = NvmeCmd::identify_namespace_list(
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cid, data.physical(), 0
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);
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let tail = queue.submit(entry);
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self.submission_queue_tail(qid as u16, tail as u16);
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}
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// println!(" - Waiting to retrieve namespace ID list");
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{
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let qid = 0;
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let queue = &mut self.completion_queues[qid];
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let (head, entry) = queue.complete_spin();
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self.completion_queue_head(qid as u16, head as u16);
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}
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// println!(" - Dumping namespace ID list");
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for &nsid in data.iter() {
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if nsid != 0 {
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nsids.push(nsid);
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}
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}
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}
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let mut namespaces = BTreeMap::new();
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for &nsid in nsids.iter() {
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//TODO: Use buffer
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let data: Dma<[u8; 4096]> = Dma::zeroed().unwrap();
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// println!(" - Attempting to identify namespace {}", nsid);
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{
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let qid = 0;
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let queue = &mut self.submission_queues[qid];
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let cid = queue.i as u16;
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let entry = NvmeCmd::identify_namespace(
|
|
cid, data.physical(), nsid
|
|
);
|
|
let tail = queue.submit(entry);
|
|
self.submission_queue_tail(qid as u16, tail as u16);
|
|
}
|
|
|
|
// println!(" - Waiting to identify namespace {}", nsid);
|
|
{
|
|
let qid = 0;
|
|
let queue = &mut self.completion_queues[qid];
|
|
let (head, entry) = queue.complete_spin();
|
|
self.completion_queue_head(qid as u16, head as u16);
|
|
}
|
|
|
|
// println!(" - Dumping identify namespace");
|
|
|
|
|
|
let size = *(data.as_ptr().offset(0) as *const u64);
|
|
let capacity = *(data.as_ptr().offset(8) as *const u64);
|
|
println!(
|
|
" - ID: {} Size: {} Capacity: {}",
|
|
nsid,
|
|
size,
|
|
capacity
|
|
);
|
|
|
|
//TODO: Read block size
|
|
|
|
namespaces.insert(nsid, NvmeNamespace {
|
|
id: nsid,
|
|
blocks: size,
|
|
block_size: 512, // TODO
|
|
});
|
|
}
|
|
|
|
for io_qid in 1..self.completion_queues.len() {
|
|
let (ptr, len) = {
|
|
let queue = &self.completion_queues[io_qid];
|
|
(queue.data.physical(), queue.data.len())
|
|
};
|
|
|
|
// println!(" - Attempting to create I/O completion queue {}", io_qid);
|
|
{
|
|
let qid = 0;
|
|
let queue = &mut self.submission_queues[qid];
|
|
let cid = queue.i as u16;
|
|
let entry = NvmeCmd::create_io_completion_queue(
|
|
cid, io_qid as u16, ptr, (len - 1) as u16
|
|
);
|
|
let tail = queue.submit(entry);
|
|
self.submission_queue_tail(qid as u16, tail as u16);
|
|
}
|
|
|
|
// println!(" - Waiting to create I/O completion queue {}", io_qid);
|
|
{
|
|
let qid = 0;
|
|
let queue = &mut self.completion_queues[qid];
|
|
let (head, entry) = queue.complete_spin();
|
|
self.completion_queue_head(qid as u16, head as u16);
|
|
}
|
|
}
|
|
|
|
for io_qid in 1..self.submission_queues.len() {
|
|
let (ptr, len) = {
|
|
let queue = &self.submission_queues[io_qid];
|
|
(queue.data.physical(), queue.data.len())
|
|
};
|
|
|
|
// println!(" - Attempting to create I/O submission queue {}", io_qid);
|
|
{
|
|
let qid = 0;
|
|
let queue = &mut self.submission_queues[qid];
|
|
let cid = queue.i as u16;
|
|
//TODO: Get completion queue ID through smarter mechanism
|
|
let entry = NvmeCmd::create_io_submission_queue(
|
|
cid, io_qid as u16, ptr, (len - 1) as u16, io_qid as u16
|
|
);
|
|
let tail = queue.submit(entry);
|
|
self.submission_queue_tail(qid as u16, tail as u16);
|
|
}
|
|
|
|
// println!(" - Waiting to create I/O submission queue {}", io_qid);
|
|
{
|
|
let qid = 0;
|
|
let queue = &mut self.completion_queues[qid];
|
|
let (head, entry) = queue.complete_spin();
|
|
self.completion_queue_head(qid as u16, head as u16);
|
|
}
|
|
}
|
|
|
|
// println!(" - Complete");
|
|
|
|
namespaces
|
|
}
|
|
|
|
unsafe fn namespace_rw(&mut self, nsid: u32, lba: u64, blocks_1: u16, write: bool) -> Result<()> {
|
|
//TODO: Get real block size
|
|
let block_size = 512;
|
|
|
|
let bytes = ((blocks_1 as u64) + 1) * block_size;
|
|
let (ptr0, ptr1) = if bytes <= 4096 {
|
|
(self.buffer_prp[0], 0)
|
|
} else if bytes <= 8192 {
|
|
(self.buffer_prp[0], self.buffer_prp[1])
|
|
} else {
|
|
(self.buffer_prp[0], (self.buffer_prp.physical() + 8) as u64)
|
|
};
|
|
|
|
{
|
|
let qid = 1;
|
|
let queue = &mut self.submission_queues[qid];
|
|
let cid = queue.i as u16;
|
|
let entry = if write {
|
|
NvmeCmd::io_write(
|
|
cid, nsid, lba, blocks_1, ptr0, ptr1
|
|
)
|
|
} else {
|
|
NvmeCmd::io_read(
|
|
cid, nsid, lba, blocks_1, ptr0, ptr1
|
|
)
|
|
};
|
|
let tail = queue.submit(entry);
|
|
self.submission_queue_tail(qid as u16, tail as u16);
|
|
}
|
|
|
|
{
|
|
let qid = 1;
|
|
let queue = &mut self.completion_queues[qid];
|
|
let (head, entry) = queue.complete_spin();
|
|
//TODO: Handle errors
|
|
self.completion_queue_head(qid as u16, head as u16);
|
|
}
|
|
|
|
Ok(())
|
|
}
|
|
|
|
pub unsafe fn namespace_read(&mut self, nsid: u32, mut lba: u64, buf: &mut [u8]) -> Result<Option<usize>> {
|
|
//TODO: Use interrupts
|
|
|
|
//TODO: Get real block size
|
|
let block_size = 512;
|
|
|
|
for chunk in buf.chunks_mut(self.buffer.len()) {
|
|
let blocks = (chunk.len() + block_size - 1) / block_size;
|
|
|
|
assert!(blocks > 0);
|
|
assert!(blocks <= 0x1_0000);
|
|
|
|
self.namespace_rw(nsid, lba, (blocks - 1) as u16, false)?;
|
|
|
|
chunk.copy_from_slice(&self.buffer[..chunk.len()]);
|
|
|
|
lba += blocks as u64;
|
|
}
|
|
|
|
Ok(Some(buf.len()))
|
|
}
|
|
|
|
pub unsafe fn namespace_write(&mut self, nsid: u32, mut lba: u64, buf: &[u8]) -> Result<Option<usize>> {
|
|
//TODO: Use interrupts
|
|
|
|
//TODO: Get real block size
|
|
let block_size = 512;
|
|
|
|
for chunk in buf.chunks(self.buffer.len()) {
|
|
let blocks = (chunk.len() + block_size - 1) / block_size;
|
|
|
|
assert!(blocks > 0);
|
|
assert!(blocks <= 0x1_0000);
|
|
|
|
self.buffer[..chunk.len()].copy_from_slice(chunk);
|
|
|
|
self.namespace_rw(nsid, lba, (blocks - 1) as u16, true)?;
|
|
|
|
lba += blocks as u64;
|
|
}
|
|
|
|
Ok(Some(buf.len()))
|
|
}
|
|
}
|