vasilito
7686729069
Extract protocol-agnostic FenceTimeline from Intel to shared src/drivers/fence.rs — atomic-based fence tracking suitable for Intel, VIRGL, and AMD drivers. Extract protocol-agnostic SyncobjManager from Intel to shared src/drivers/syncobj.rs — syncobj create/destroy/signal/reset/ wait/query and sync_file fd export/import. Wire both into VirtioDriver: - Add FenceTimeline + SyncobjManager fields - Implement all 5 GpuDriver syncobj trait methods (create, destroy, wait, export_fd, import_fd) - Track fence seqnos in virgl_submit_3d (allocate before submit, signal after completion) Intel fence.rs and syncobj.rs converted to thin re-export modules pointing at shared sources — no behavioral change for Intel driver. This gives Mesa VIRGL userspace the standard DRM syncobj API for GPU/compositor synchronization.
32 lines
1.0 KiB
Plaintext
32 lines
1.0 KiB
Plaintext
dnl Check whether limits.h has needed features.
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dnl Copyright 2016-2017 Free Software Foundation, Inc.
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dnl This file is free software; the Free Software Foundation
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dnl gives unlimited permission to copy and/or distribute it,
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dnl with or without modifications, as long as this notice is preserved.
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dnl From Paul Eggert.
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AC_DEFUN_ONCE([gl_LIMITS_H],
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[
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gl_CHECK_NEXT_HEADERS([limits.h])
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AC_CACHE_CHECK([whether limits.h has ULLONG_WIDTH etc.],
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[gl_cv_header_limits_width],
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[AC_COMPILE_IFELSE(
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[AC_LANG_PROGRAM([[#ifndef __STDC_WANT_IEC_60559_BFP_EXT__
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#define __STDC_WANT_IEC_60559_BFP_EXT__ 1
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#endif
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#include <limits.h>
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int ullw = ULLONG_WIDTH;]])],
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[gl_cv_header_limits_width=yes],
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[gl_cv_header_limits_width=no])])
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if test "$gl_cv_header_limits_width" = yes; then
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LIMITS_H=
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else
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LIMITS_H=limits.h
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fi
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AC_SUBST([LIMITS_H])
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AM_CONDITIONAL([GL_GENERATE_LIMITS_H], [test -n "$LIMITS_H"])
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])
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