vasilito
7686729069
Extract protocol-agnostic FenceTimeline from Intel to shared src/drivers/fence.rs — atomic-based fence tracking suitable for Intel, VIRGL, and AMD drivers. Extract protocol-agnostic SyncobjManager from Intel to shared src/drivers/syncobj.rs — syncobj create/destroy/signal/reset/ wait/query and sync_file fd export/import. Wire both into VirtioDriver: - Add FenceTimeline + SyncobjManager fields - Implement all 5 GpuDriver syncobj trait methods (create, destroy, wait, export_fd, import_fd) - Track fence seqnos in virgl_submit_3d (allocate before submit, signal after completion) Intel fence.rs and syncobj.rs converted to thin re-export modules pointing at shared sources — no behavioral change for Intel driver. This gives Mesa VIRGL userspace the standard DRM syncobj API for GPU/compositor synchronization.
38 lines
1.2 KiB
Plaintext
38 lines
1.2 KiB
Plaintext
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#------------------------------------------------------------------------------
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# $File: xo65,v 1.5 2022/07/17 15:36:20 christos Exp $
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# https://cc65.github.io/doc/sim65.html
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# xo65 object files
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# From: "Ullrich von Bassewitz" <uz@cc65.org>
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#
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0 string \x55\x7A\x6E\x61 xo65 object,
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>4 leshort x version %d,
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>6 leshort&0x0001 =0x0001 with debug info
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>6 leshort&0x0001 =0x0000 no debug info
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# xo65 library files
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0 string \x6E\x61\x55\x7A xo65 library,
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>4 leshort x version %d
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# o65 object files
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0 string \x01\x00\x6F\x36\x35 o65
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>6 leshort&0x1000 =0x0000 executable,
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>6 leshort&0x1000 =0x1000 object,
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>5 byte x version %d,
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>6 leshort&0x8000 =0x8000 65816,
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>6 leshort&0x8000 =0x0000 6502,
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>6 leshort&0x2000 =0x2000 32 bit,
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>6 leshort&0x2000 =0x0000 16 bit,
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>6 leshort&0x4000 =0x4000 page reloc,
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>6 leshort&0x4000 =0x0000 byte reloc,
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>6 leshort&0x0003 =0x0000 alignment 1
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>6 leshort&0x0003 =0x0001 alignment 2
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>6 leshort&0x0003 =0x0002 alignment 4
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>6 leshort&0x0003 =0x0003 alignment 256
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# sim65 executable files
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0 string \x73\x69\x6d\x36\x35 sim65 executable,
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>5 byte x version %d,
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>6 leshort&0x0000 =0x0000 6502
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>6 leshort&0x0001 =0x0001 65C02
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