vasilito
7686729069
Extract protocol-agnostic FenceTimeline from Intel to shared src/drivers/fence.rs — atomic-based fence tracking suitable for Intel, VIRGL, and AMD drivers. Extract protocol-agnostic SyncobjManager from Intel to shared src/drivers/syncobj.rs — syncobj create/destroy/signal/reset/ wait/query and sync_file fd export/import. Wire both into VirtioDriver: - Add FenceTimeline + SyncobjManager fields - Implement all 5 GpuDriver syncobj trait methods (create, destroy, wait, export_fd, import_fd) - Track fence seqnos in virgl_submit_3d (allocate before submit, signal after completion) Intel fence.rs and syncobj.rs converted to thin re-export modules pointing at shared sources — no behavioral change for Intel driver. This gives Mesa VIRGL userspace the standard DRM syncobj API for GPU/compositor synchronization.
82 lines
3.0 KiB
Plaintext
82 lines
3.0 KiB
Plaintext
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#------------------------------------------------------------------------------
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# $File: xilinx,v 1.12 2024/09/04 19:06:12 christos Exp $
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# This is Aaron's attempt at a MAGIC file for Xilinx .bit files.
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# Xilinx-Magic@RevRagnarok.com
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# Got the info from FPGA-FAQ 0026
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#
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# Rewritten to use pstring/H instead of hardcoded lengths by O. Freyermuth,
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# fixes at least reading of bitfiles from Spartan 2, 3, 6.
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# http://www.fpga-faq.com/FAQ_Pages/0026_Tell_me_about_bit_files.htm
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#
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# First there is the sync header and its length
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0 beshort 0x0009
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>2 belong =0x0ff00ff0
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>>&0 belong =0x0ff00ff0
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>>>&0 byte =0x00
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>>>>&1 beshort =0x0001
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>>>>>&3 string a Xilinx BIT data
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# Next is a Pascal-style string with the NCD name. We want to capture that.
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>>>>>>&0 pstring/H x - from %s
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# And then 'b'
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>>>>>>>&1 string b
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# Then the model / part number:
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>>>>>>>>&0 pstring/H x - for %s
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# Then 'c'
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>>>>>>>>>&1 string c
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# Then the build-date
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>>>>>>>>>>&0 pstring/H x - built %s
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# Then 'd'
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>>>>>>>>>>>&1 string d
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# Then the build-time
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>>>>>>>>>>>>&0 pstring/H x \b(%s)
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# Then 'e'
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>>>>>>>>>>>>>&1 string e
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# And length of data
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>>>>>>>>>>>>>>&0 belong x - data length %#x
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# Raw bitstream files
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0 long 0xffffffff
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>&0 belong 0xaa995566 Xilinx RAW bitstream (.BIN)
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# AXLF (xclbin) files used by AMD/Xilinx accelerators.
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# The file format is defined by XRT source tree:
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# https://github.com/Xilinx/XRT/blob/master/src/runtime_src/core/include/xclbin.h
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# Display file size, creation date, accelerator shell name, xclbin uuid and
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# number of sections.
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0 string xclbin2 AMD/Xilinx accelerator AXLF (xclbin) file
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>0x130 lequad x \b, %lld bytes
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>0x138 leqdate x \b, created %s
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>0x160 string >0 \b, shell "%.64s"
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>0x1a0 ubelong x \b, uuid %08x
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>0x1a4 ubeshort x \b-%04x
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>0x1a6 ubeshort x \b-%04x
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>0x1a8 ubeshort x \b-%04x
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>0x1aa ubelong x \b-%08x
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>0x1ae ubeshort x \b%04x
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>0x1c0 lelong x \b, %d sections
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# Xilinx Boot Image files
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# File format spec is from Xilinx UG1283
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# https://docs.xilinx.com/r/en-US/ug1283-bootgen-user-guide
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0x20 lelong 0xAA995566
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>0x24 lelong 0x584c4e58 Xilinx Boot Image
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>>0x0 lelong 0xEAFFFFFE \b, 32-bit
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>>0x0 lelong 0x14000000 \b, 64-bit
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>>0x28 lelong 0x00000000 \b, unencrypted
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>>0x28 lelong 0xA5C3C5A5 \b, black key in efuse
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>>0x28 lelong 0xA5C3C5A7 \b, obfuscated key in efuse
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>>0x28 lelong 0x3A5C3C5A \b, red key in bbram
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>>0x28 lelong 0xA5C3C5A3 \b, efuse red key in efuse
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>>0x28 lelong 0xA35C7CA5 \b, obfuscated key in boot header
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>>0x28 lelong 0xA3A5C3C5 \b, user key in boot header
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>>0x28 lelong 0xA35C7C53 \b, black key in boot header
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>>0x2C lelong 0x01010000 \b, Zynq 7000 SoC
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!:mime application/x-xilinx-boot-zynq
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>>>0x34 ulelong >0 \b, FSBL size %#x bytes
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>>0x2C lelong !0x01010000 \b, Zynq UltraScale+ MPSoC
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!:mime application/x-xilinx-boot-zynqmp
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>>>0x34 ulelong >0 \b, PMU size %#x bytes
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>>>0x3C ulelong >0 \b, FSBL size %#x bytes
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