vasilito
7686729069
Extract protocol-agnostic FenceTimeline from Intel to shared src/drivers/fence.rs — atomic-based fence tracking suitable for Intel, VIRGL, and AMD drivers. Extract protocol-agnostic SyncobjManager from Intel to shared src/drivers/syncobj.rs — syncobj create/destroy/signal/reset/ wait/query and sync_file fd export/import. Wire both into VirtioDriver: - Add FenceTimeline + SyncobjManager fields - Implement all 5 GpuDriver syncobj trait methods (create, destroy, wait, export_fd, import_fd) - Track fence seqnos in virgl_submit_3d (allocate before submit, signal after completion) Intel fence.rs and syncobj.rs converted to thin re-export modules pointing at shared sources — no behavioral change for Intel driver. This gives Mesa VIRGL userspace the standard DRM syncobj API for GPU/compositor synchronization.
23 lines
768 B
Plaintext
23 lines
768 B
Plaintext
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#------------------------------------------------------------------------------
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# $File: llvm,v 1.10 2023/03/11 17:54:17 christos Exp $
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# llvm: file(1) magic for LLVM byte-codes
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# URL: https://llvm.org/docs/BitCodeFormat.html
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# From: Al Stone <ahs3@fc.hp.com>
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0 string llvm LLVM byte-codes, uncompressed
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0 string llvc0 LLVM byte-codes, null compression
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0 string llvc1 LLVM byte-codes, gzip compression
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0 string llvc2 LLVM byte-codes, bzip2 compression
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0 string CPCH LLVM Pre-compiled header file
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0 lelong 0x0b17c0de LLVM bitcode, wrapper
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# Are these Mach-O ABI values? They appear to be.
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>16 lelong 0x01000007 x86_64
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>16 lelong 0x00000007 i386
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>16 lelong 0x00000012 ppc
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>16 lelong 0x01000012 ppc64
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>16 lelong 0x0000000c arm
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0 string BC\xc0\xde LLVM IR bitcode
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