vasilito
7686729069
Extract protocol-agnostic FenceTimeline from Intel to shared src/drivers/fence.rs — atomic-based fence tracking suitable for Intel, VIRGL, and AMD drivers. Extract protocol-agnostic SyncobjManager from Intel to shared src/drivers/syncobj.rs — syncobj create/destroy/signal/reset/ wait/query and sync_file fd export/import. Wire both into VirtioDriver: - Add FenceTimeline + SyncobjManager fields - Implement all 5 GpuDriver syncobj trait methods (create, destroy, wait, export_fd, import_fd) - Track fence seqnos in virgl_submit_3d (allocate before submit, signal after completion) Intel fence.rs and syncobj.rs converted to thin re-export modules pointing at shared sources — no behavioral change for Intel driver. This gives Mesa VIRGL userspace the standard DRM syncobj API for GPU/compositor synchronization.
37 lines
1.1 KiB
Plaintext
37 lines
1.1 KiB
Plaintext
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#------------------------------------------------------------------------------
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# $File: flif,v 1.1 2015/11/23 22:04:36 christos Exp $
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# flif: Magic data for file(1) command.
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# FLIF (Free Lossless Image Format)
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0 string FLIF FLIF
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>4 string <H image data
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>>6 beshort x \b, %u
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>>8 beshort x \bx%u
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>>5 string 1 \b, 8-bit/color,
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>>5 string 2 \b, 16-bit/color,
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>>4 string 1 \b, grayscale, non-interlaced
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>>4 string 3 \b, RGB, non-interlaced
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>>4 string 4 \b, RGBA, non-interlaced
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>>4 string A \b, grayscale
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>>4 string C \b, RGB, interlaced
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>>4 string D \b, RGBA, interlaced
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>4 string >H \b, animation data
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>>5 ubyte <255 \b, %i frames
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>>>7 beshort x \b, %u
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>>>9 beshort x \bx%u
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>>>6 string =1 \b, 8-bit/color
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>>>6 string =2 \b, 16-bit/color
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>>5 ubyte 0xFF
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>>>6 beshort x \b, %i frames,
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>>>9 beshort x \b, %u
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>>>11 beshort x \bx%u
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>>>8 string =1 \b, 8-bit/color
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>>>8 string =2 \b, 16-bit/color
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>>4 string =Q \b, grayscale, non-interlaced
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>>4 string =S \b, RGB, non-interlaced
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>>4 string =T \b, RGBA, non-interlaced
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>>4 string =a \b, grayscale
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>>4 string =c \b, RGB, interlaced
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>>4 string =d \b, RGBA, interlaced
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