613 lines
24 KiB
Plaintext
613 lines
24 KiB
Plaintext
--------------------------------------------------------------------------------
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-- light52_muldiv.vhdl -- Simple multiplier/divider module.
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--------------------------------------------------------------------------------
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-- The 8051 mul and div instructions are both unsigned and operands are 8 bit.
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--
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-- This module implements the division as a sequential state machine which takes
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-- 8 cycles to complete.
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-- The multiplier can be implemented as sequential or as combinational, in which
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-- case it will use a DSP block in those architectures that support it.
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-- No attempt has been made to make this module generic or reusable.
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--
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-- If you want a combinational multiplier but don't want to waste a DSP block
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-- in this module, you need to modify this file adding whatever synthesis
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-- pragmas your tool of choice needs.
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--
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-- Note that unlike the division state machine, the combinational product logic
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-- is always operating: when SEQUENTIAL_MULTIPLIER=true, prod_out equals
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-- data_a * data_b with a latency of 1 clock cycle, and mul_ready is hardwired
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-- to '1'.
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--
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-- FIXME explain division algorithm.
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--------------------------------------------------------------------------------
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-- GENERICS:
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--
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-- SEQUENTIAL_MULTIPLIER -- Sequential vs. combinational multiplier.
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-- When true, a sequential implementation will be used for the multiplier,
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-- which will usually save a lot of logic or a dedicated multiplier.
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-- When false, a combinational registered multiplier will be used.
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--
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--------------------------------------------------------------------------------
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-- INTERFACE SIGNALS:
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--
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-- clk : Clock, active rising edge.
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-- reset : Synchronous reset. Clears only the control registers not
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-- visible to the programmer -- not the output registers.
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--
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-- data_a : Numerator input, should be connected to the ACC register.
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-- data_b : Denominator input, should be connected to the B register.
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-- start : Assert for 1 cycle to start the division state machine
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-- (and the product if SEQUENTIAL_MULTIPLIER=true);
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--
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-- prod_out : Product output, valid only when mul_ready='1'.
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-- quot_out : Quotient output, valid only when div_ready='1'.
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-- rem_out : Remainder output, valid only when div_ready='1'.
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-- div_ov_out : Division overflow flag, valid only when div_ready='1'.
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-- mul_ov_out : Product overflow flag, valid only when mul_ready='1'.
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--
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-- mul_ready : Asserted permanently if SEQUENTIAL_MULTIPLIER=false.
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-- div_ready : Deasserted the cycle after start is asserted.
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-- Asserted when the division has completed.
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--
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--------------------------------------------------------------------------------
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-- Copyright (C) 2012 Jose A. Ruiz
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- either version 2.1 of the License, or (at your option) any
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-- later version.
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--
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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--
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-- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- from http://www.opencores.org/lgpl.shtml
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.light52_pkg.all;
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use work.light52_ucode_pkg.all;
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entity <beginfold id='1'>light52_muldiv</beginfold id='1'> is
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generic (
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SEQUENTIAL_MULTIPLIER : boolean := false
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);
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port(
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clk : in std_logic;
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reset : in std_logic;
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data_a : in t_byte;
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data_b : in t_byte;
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start : in std_logic;
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prod_out : out t_word;
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quot_out : out t_byte;
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rem_out : out t_byte;
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div_ov_out : out std_logic;
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mul_ov_out : out std_logic;
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mul_ready : out std_logic;
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div_ready : out std_logic
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);
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<endfold id='1'>end entity light52_muldiv;</endfold id='1'>
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architecture <beginfold id='2'>sequential</beginfold id='2'> of light52_muldiv is
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signal bit_ctr : integer range 0 to 8;
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signal b_shift_reg : t_word;
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signal den_ge_256 : std_logic;
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signal num_ge_den : std_logic;
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signal sub_num : std_logic;
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signal denominator : t_byte;
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signal rem_reg : t_byte;
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signal quot_reg : t_byte;
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signal prod_reg : t_word;
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signal ready : std_logic;
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signal load_regs : std_logic;
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begin
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-- Control logic ---------------------------------------------------------------
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control_counter: <beginfold id='3'>process</beginfold id='3'>(clk)
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alias sig is <<signal g_test(0).i_test.sig : std_logic>>;
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begin
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<beginfold id='4'>if</beginfold id='4'> clk'event and clk='1' then
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<beginfold id='4'>if</beginfold id='4'> reset='1' then
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bit_ctr <= 8;
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else
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<beginfold id='4'>if</beginfold id='4'> load_regs='1' then
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bit_ctr <= 0;
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elsif bit_ctr /= 8 then
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bit_ctr <= bit_ctr + 1;
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<endfold id='4'>end if;</endfold id='4'>
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<endfold id='4'>end if;</endfold id='4'>
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<endfold id='4'>end if;</endfold id='4'>
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<endfold id='3'>end process control_counter;</endfold id='3'>
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-- Internal signal ready is asserted after 8 cycles.
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-- The sequential multiplier will use this signal too, IF it takes 8 cycles.
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ready <= '1' when bit_ctr >= 8 else '0';
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---- Divider logic -------------------------------------------------------------
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-- What we do is a simple base-2 'shift-and-subtract' algorithm that takes
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-- 8 cycles to complete. We can get away with this because we deal with unsigned
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-- numbers only.
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divider_registers: <beginfold id='3'>process</beginfold id='3'>(clk)
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begin
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<beginfold id='4'>if</beginfold id='4'> clk'event and clk='1' then
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-- denominator shift register
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<beginfold id='4'>if</beginfold id='4'> load_regs='1' then
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b_shift_reg <= "0" & data_b & "0000000";
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-- Division overflow can be determined upon loading B reg data.
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-- OV will be raised only on div-by-zero.
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<beginfold id='4'>if</beginfold id='4'> data_b=X"00" then
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div_ov_out <= '1';
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else
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div_ov_out <= '0';
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<endfold id='4'>end if;</endfold id='4'>
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else
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b_shift_reg <= "0" & b_shift_reg(b_shift_reg'high downto 1);
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<endfold id='4'>end if;</endfold id='4'>
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-- numerator register
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<beginfold id='4'>if</beginfold id='4'> load_regs='1' then
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rem_reg <= data_a;
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elsif bit_ctr/=8 and sub_num='1' then
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rem_reg <= rem_reg - denominator;
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<endfold id='4'>end if;</endfold id='4'>
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--- quotient register
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<beginfold id='4'>if</beginfold id='4'> load_regs='1' then
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quot_reg <= (others => '0');
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elsif bit_ctr/=8 then
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quot_reg <= quot_reg(quot_reg'high-1 downto 0) & sub_num;
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<endfold id='4'>end if;</endfold id='4'>
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load_regs <= start;
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<endfold id='4'>end if;</endfold id='4'>
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<endfold id='3'>end process divider_registers;</endfold id='3'>
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denominator <= b_shift_reg(7 downto 0);
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-- The 16-bit comparison between b_shift_reg (denominator) and the zero-extended
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-- rem_reg (numerator) can be simplified by splitting it in 2:
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-- If the shifted denominator high byte is not zero, it is >=256...
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den_ge_256 <= '1' when b_shift_reg(15 downto 8) /= X"00" else '0';
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-- ...otherwise we need to compare the low bytes.
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num_ge_den <= '1' when rem_reg >= denominator else '0';
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sub_num <= '1' when den_ge_256='0' and num_ge_den='1' else '0';
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quot_out <= quot_reg;
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prod_out <= prod_reg;
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rem_out <= rem_reg;
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div_ready <= ready;
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---- Multiplier logic ----------------------------------------------------------
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---- Combinational multiplier -----------------------------
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multiplier_combinational: <beginfold id='4'>if</beginfold id='4'> not SEQUENTIAL_MULTIPLIER generate
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registered_combinational_multiplier:<beginfold id='3'>process</beginfold id='3'>(clk)
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begin
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<beginfold id='4'>if</beginfold id='4'> clk'event and clk='1' then
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prod_reg <= data_a * data_b; -- t_byte is unsigned
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<endfold id='4'>end if;</endfold id='4'>
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<endfold id='3'>end process registered_combinational_multiplier;</endfold id='3'>
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-- The multiplier output is valid in the cycle after the operands are loaded,
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-- so by the time MUL is executed it's already done.
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mul_ready <= '1';
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mul_ov_out <= '1' when prod_reg(15 downto 8)/=X"00" else '0';
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prod_out <= prod_reg;
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<endfold id='4'>end generate multiplier_combinational;</endfold id='4'>
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---- Sequential multiplier --------------------------------
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multiplier_sequential: <beginfold id='4'>if</beginfold id='4'> SEQUENTIAL_MULTIPLIER generate
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assert false
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report "Sequential multiplier implementation not done yet."&
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" Use combinational implementation."
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severity failure;
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<endfold id='4'>end generate multiplier_sequential;</endfold id='4'>
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<endfold id='2'>end sequential;</endfold id='2'>
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with Types; use Types;
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with Files_Map;
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package <beginfold id='5'>fixed_pkg</beginfold id='5'> is new IEEE.fixed_generic_pkg
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generic map <beginfold id='6'>(</beginfold id='6'>
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fixed_overflow_style => IEEE.fixed_float_types.fixed_saturate,
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fixed_guard_bits => 3,
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no_warning => false
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<endfold id='6'>)</endfold id='6'><endfold id='5'>;</endfold id='5'>
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package <beginfold id='5'>p</beginfold id='5'> is
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type int_ptr is access integer;
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type rec is <beginfold id='7'>record</beginfold id='7'>
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data : std_logic_vector(31 downto 0);
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ack : std_logic;
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value : integer;
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link : rec_ptr;
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<endfold id='7'>end record;</endfold id='7'>
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type int_vec is array (integer range <>) of integer;
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type int_vec_ptr is access int_vec;
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<beginfold id='8'>procedure</beginfold id='8'> UNIFORM(variable SEED1, SEED2 : inout POSITIVE; variable X : out REAL)<endfold id='8'>;</endfold id='8'>
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constant def_arr : t_int_array := (0 to 2 => 10);
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-- type range
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type newInt is range -4 to 3;
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type CAPACITY is range 0 to 1E5 <beginfold id='9'>units</beginfold id='9'>
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pF;
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nF = 1000 pF;
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<endfold id='9'>end units;</endfold id='9'>
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-- type protected
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type prot is <beginfold id='10'>protected</beginfold id='10'>
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function meth(a : int) return bit;
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<endfold id='10'>end protected;</endfold id='10'>
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-- type protected body
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type prot is <beginfold id='10'>protected</beginfold id='10'> body
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variable var : positive;
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constant const : boolean;
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function meth(a : int) return bit <beginfold id='11'>is</beginfold id='11'>
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begin
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<endfold id='11'>end function;</endfold id='11'>
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<endfold id='10'>end protected body;</endfold id='10'>
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function \?=\ (L, R : BOOLEAN) return BOOLEAN;
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<endfold id='5'>end package;</endfold id='5'>
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package body <beginfold id='12'>p</beginfold id='12'> is
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function \?=\ (L, R : BOOLEAN) return BOOLEAN <beginfold id='11'>is</beginfold id='11'>
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begin
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<beginfold id='4'>if</beginfold id='4'> not (format(format'left) = '%') then
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report "to_string: Illegal format string """ & format & '"'
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severity error;
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return "";
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<endfold id='4'>end if;</endfold id='4'>
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return L = R;
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<endfold id='11'>end function \?=\;</endfold id='11'>
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<beginfold id='8'>procedure</beginfold id='8'> test is
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variable v : int_ptr;
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variable i : integer;
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<endfold id='8'></endfold id='8'><beginfold id='8'>begin</beginfold id='8'>
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v := null;
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deallocate(v);
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v := new integer;
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v := new integer'(5);
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v.all := 5;
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r.all.value := 1;
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a := new int_vec(1 to 3);
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a.all(5) := 2;
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a(1 to 2) := (1, 2);
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s := new string'("");
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<endfold id='8'>end procedure;</endfold id='8'>
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<beginfold id='8'>procedure</beginfold id='8'> test2(x : inout rec_ptr) is
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<endfold id='8'></endfold id='8'><beginfold id='8'>begin</beginfold id='8'>
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x.value := x.value + 1;
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<endfold id='8'>end procedure;</endfold id='8'>
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<beginfold id='8'>procedure</beginfold id='8'> test3 is
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type a;
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type a is access integer;
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variable v : a;
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<endfold id='8'></endfold id='8'><beginfold id='8'>begin</beginfold id='8'>
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<endfold id='8'>end procedure;</endfold id='8'>
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type int_ptr_array is array (integer range <>) of int_ptr;
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<beginfold id='8'>procedure</beginfold id='8'> tets4 is
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type bvp is access bit_vector;
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variable y : int_ptr(1 to 3) := int_ptr'(null);
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<endfold id='8'></endfold id='8'><beginfold id='8'>begin</beginfold id='8'>
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<endfold id='8'>end procedure;</endfold id='8'>
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<beginfold id='8'>procedure</beginfold id='8'> Restore_Origin (Mark : Instance_Index_Type) is
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<endfold id='8'></endfold id='8'><beginfold id='8'>begin</beginfold id='8'>
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for I in reverse Mark + 1 .. Prev_Instance_Table.Last <beginfold id='13'>loop</beginfold id='13'>
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<beginfold id='14'>declare</beginfold id='14'>
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El : Instance_Entry_Type renames Prev_Instance_Table.Table (I);
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begin
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Origin_Table.Table (El.N) := El.Old_Origin;
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<endfold id='14'>end;</endfold id='14'>
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<endfold id='13'>end loop;</endfold id='13'>
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Prev_Instance_Table.Set_Last (Mark);
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<endfold id='8'>end Restore_Origin;</endfold id='8'>
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-- Instantiate a list. Simply create a new list and instantiate nodes of
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-- that list.
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function Instantiate_Iir_List (L : Iir_List; Is_Ref : Boolean)
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return Iir_List
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<beginfold id='11'>is</beginfold id='11'>
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Res : Iir_List;
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El : Iir;
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begin
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<beginfold id='15'>case</beginfold id='15'> to_integer(unsigned(CTRL_REF(x*4+3 downto x*4))) is
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when Null_Iir_List
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| Iir_List_All <beginfold id='16'>=></beginfold id='16'>
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return L;
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<endfold id='16'>when</endfold id='16'> others <beginfold id='16'>=></beginfold id='16'>
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It := List_Iterate (L);
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while Is_Valid (It) <beginfold id='13'>loop</beginfold id='13'>
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El := Get_Element (It);
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Append_Element (Res, Instantiate_Iir (El, Is_Ref));
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<endfold id='13'>end loop;</endfold id='13'>
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for I in Flist_First .. Flist_Last (L) <beginfold id='13'>loop</beginfold id='13'>
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Set_Nth_Element (Res, I, Instantiate_Iir (El, Is_Ref));
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<endfold id='13'>end loop;</endfold id='13'>
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return Res;
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<endfold id='16'></endfold id='16'><endfold id='15'>end case;</endfold id='15'>
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<endfold id='11'>end Instantiate_Iir_List;</endfold id='11'>
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<endfold id='12'>end package body;</endfold id='12'>
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-- Library bar
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context foo.test_context;
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context <beginfold id='17'>foo</beginfold id='17'> is
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context foo.test_context;
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<endfold id='17'>end context foo;</endfold id='17'>
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entity <beginfold id='1'>concat</beginfold id='1'> is
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<endfold id='1'>end entity;</endfold id='1'>
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entity <beginfold id='1'>foo</beginfold id='1'> is
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port (
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x : in my_int );
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<endfold id='1'>end entity;</endfold id='1'>
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architecture <beginfold id='2'>t</beginfold id='2'> of concat is
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type int_array is array (integer range <>) of integer;
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type small is range 1 to 3;
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component <beginfold id='18'>or_entity</beginfold id='18'> is
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port(
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input_1: in std_logic;
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output: out std_logic
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);
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<endfold id='18'>end component;</endfold id='18'>
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begin
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<beginfold id='3'>process</beginfold id='3'>
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variable s : string(1 to 5);
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variable t : int_array(1 to 2);
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variable c : bit_vector(1 to 4);
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begin
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x := ( 1, 2, 3 );
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z := x & y;
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w := 1 & x;
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s := 'h' & string'("ello");
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assert "10" = (b(1) & "0");
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wait;
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<endfold id='3'>end process;</endfold id='3'>
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function CounterVal(Seconds : integer := 0) return integer <beginfold id='11'>is</beginfold id='11'>
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variable TotalSeconds : interger;
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begin
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TotalSeconds := Seconds + Minutes * 60;
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return TotalSeconds * ClockFrequencyHz -1;
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<endfold id='11'>end function;</endfold id='11'>
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type enum_type is (a, b, c, ..., z);
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type int_array is array(3 downto 0) of integer;
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subtype addr_int is integer range 0 to 65535;
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subtype sub_enum_type is enum_type range a to m;
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inst1: entity <beginfold id='19'>work.counter1</beginfold id='19'>(rtl)
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generic map <beginfold id='6'>(</beginfold id='6'>BITS1 => 8<endfold id='6'>)</endfold id='6'>
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port map <beginfold id='6'>(</beginfold id='6'>
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clk1 => Clock,
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DATA_OUT => pwm_data_o(3 downto 5),
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COMP_IN(1 downto 0) => compensate_i,
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WRITE_IN => (others => '0')
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<endfold id='6'>)</endfold id='6'><endfold id='19'>;</endfold id='19'>
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inst2: component <beginfold id='19'>counter2</beginfold id='19'>
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generic map <beginfold id='6'>(</beginfold id='6'>BITS1 => 8<endfold id='6'>)</endfold id='6'>
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port map <beginfold id='6'>(</beginfold id='6'>clk1 => Clock<endfold id='6'>)</endfold id='6'><endfold id='19'>;</endfold id='19'>
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inst3: configuration <beginfold id='19'>counter3</beginfold id='19'>
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generic map <beginfold id='6'>(</beginfold id='6'>BITS1 => 8<endfold id='6'>)</endfold id='6'>
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|
port map <beginfold id='6'>(</beginfold id='6'>clk1 => Clock<endfold id='6'>)</endfold id='6'><endfold id='19'>;</endfold id='19'>
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|
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|
THE_PWM_GEN : <beginfold id='19'>pwm_generator</beginfold id='19'>
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|
generic map<beginfold id='6'>(</beginfold id='6'>
|
|
dsfds => ds
|
|
<endfold id='6'>)</endfold id='6'>
|
|
port map<beginfold id='6'>(</beginfold id='6'>
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|
CLK => clk_i,
|
|
DATA_IN => pwm_data_i,
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|
DATA_OUT => pwm_data_o(3 downto 5),
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|
COMP_IN(1 downto 0) => compensate_i,
|
|
WRITE_IN => (others => '0')
|
|
<endfold id='6'>)</endfold id='6'><endfold id='19'>;</endfold id='19'>
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|
|
|
<endfold id='2'>end architecture;</endfold id='2'>
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|
|
|
architecture <beginfold id='2'>a2</beginfold id='2'> of e is
|
|
function ">"(a, b: my_int) return boolean;
|
|
begin
|
|
<beginfold id='3'>process</beginfold id='3'> is
|
|
variable x, y : my_int;
|
|
begin
|
|
assert x > y;
|
|
assert x < y; -- Error
|
|
<endfold id='3'>end process;</endfold id='3'>
|
|
|
|
billowitch_tc586: <beginfold id='10'>block</beginfold id='10'> is
|
|
type real_cons_vector is array (15 downto 0) of real;
|
|
type real_cons_vector_file is file of real_cons_vector;
|
|
constant C19 : real_cons_vector := (others => 3.0);
|
|
begin
|
|
<endfold id='10'>end block;</endfold id='10'>
|
|
<endfold id='2'>end architecture;</endfold id='2'>
|
|
|
|
architecture <beginfold id='2'>arch</beginfold id='2'> of ent is
|
|
begin
|
|
LL: <beginfold id='4'>if</beginfold id='4'> test=10 generate
|
|
begin
|
|
end;
|
|
elsif test=5 generate
|
|
begin
|
|
end;
|
|
<endfold id='4'>end generate;</endfold id='4'>
|
|
|
|
LL: <beginfold id='4'>if</beginfold id='4'> l1: SPEED = "fast" generate
|
|
elsif test=5 generate
|
|
<endfold id='4'>end generate;</endfold id='4'>
|
|
<endfold id='2'>end architecture arch;</endfold id='2'>
|
|
|
|
|
|
architecture <beginfold id='2'>thing_arch</beginfold id='2'> of designthing is
|
|
|
|
component <beginfold id='18'>pwm_generator</beginfold id='18'>
|
|
port(
|
|
CLK : in std_logic;
|
|
DATA_IN : in std_logic_vector(15 downto 0);
|
|
);
|
|
<endfold id='18'>end component pwm_generator;</endfold id='18'>
|
|
|
|
attribute NOM_FREQ : string;
|
|
attribute NOM_FREQ of clk_source : label is "133.00";
|
|
signal clk_i : std_logic;
|
|
|
|
begin
|
|
|
|
gen_no_comp: <beginfold id='4'>if</beginfold id='4'> TEMP = 0 generate
|
|
compensate_i <= (others => '0');
|
|
<endfold id='4'>end generate;</endfold id='4'>
|
|
|
|
gen_no_comp: <beginfold id='13'>for</beginfold id='13'> i in 0 to TEMP generate
|
|
compensate_i <= (others => '0') after 10 ns;
|
|
compensate_i <= (others => '0') ;
|
|
<endfold id='13'>end generate;</endfold id='13'>
|
|
|
|
---------------------------------------------------------------------------
|
|
-- LED blinking when activity on inputs
|
|
---------------------------------------------------------------------------
|
|
PROC_TIMER : <beginfold id='3'>process</beginfold id='3'> begin
|
|
wait until rising_edge(clk_i);
|
|
timer <= timer + 1;
|
|
wait for 10 ns;
|
|
leds <= (last_inp xor inp_status(3 downto 0)) or leds or last_leds;
|
|
<beginfold id='4'>if</beginfold id='4'> timer = 0 then
|
|
leds <= not inp_status(3 downto 0);
|
|
last_leds <= x"0";
|
|
elsif gf then
|
|
fdsa <= '1';
|
|
<endfold id='4'>end if;</endfold id='4'>
|
|
|
|
xz: for x in 0 to 7 <beginfold id='13'>loop</beginfold id='13'>
|
|
dsadf;
|
|
<endfold id='13'>end loop;</endfold id='13'>
|
|
|
|
<beginfold id='15'>case</beginfold id='15'> c is
|
|
when XXX <beginfold id='16'>=></beginfold id='16'>
|
|
c <= 1;
|
|
d <= 21321;
|
|
<endfold id='16'>when</endfold id='16'> YYYY <beginfold id='16'>=></beginfold id='16'>
|
|
c <= 2;
|
|
<endfold id='16'></endfold id='16'><endfold id='15'>end case;</endfold id='15'>
|
|
<endfold id='3'>end process;</endfold id='3'>
|
|
|
|
|
|
generate_with_begin: <beginfold id='4'>if</beginfold id='4'> TEMP = 0 generate
|
|
signal : test : std_logic;
|
|
begin
|
|
compensate_i <= (others => '0');
|
|
<beginfold id='4'>if</beginfold id='4'> timer = 0 then
|
|
leds <= not inp_status(3 downto 0);
|
|
last_leds <= x"0";
|
|
elsif gf then
|
|
fdsa <= '1';
|
|
<endfold id='4'>end if;</endfold id='4'>
|
|
<endfold id='4'>end generate generate_with_begin;</endfold id='4'>
|
|
|
|
PROC_TIMER : <beginfold id='3'>process</beginfold id='3'>
|
|
variable x : std_logic;
|
|
begin
|
|
x := '0';
|
|
<endfold id='3'>end process PROC_TIMER;</endfold id='3'>
|
|
|
|
<endfold id='2'>end</endfold id='2'> architecture thing_arc; --this is not correct (wrong name)
|
|
|
|
1+1
|
|
2ns
|
|
|
|
1_2_3
|
|
12_3
|
|
1.2
|
|
1.2_3
|
|
1_3.2_3
|
|
12_3e+1
|
|
12_3e-1
|
|
12_3e1_1
|
|
12_3.4e1_1
|
|
12_3e1_
|
|
12_3e
|
|
|
|
2#1_2_3#E+8
|
|
2#1_2.3#E+8
|
|
2#1_f2.3#
|
|
|
|
3.14159_26536 -- A literal of type universal_real.
|
|
5280 -- A literal of type universal_integer.
|
|
10.7 ns -- A literal of a physical type.
|
|
O"4777" -- A bit string literal.
|
|
"54LS281" -- A string literal.
|
|
"" -- A string literal representing a null array.
|
|
B"1111_1111_1111" -- Equivalent to the string literal "111111111111".
|
|
X"FFF" -- Equivalent to B"1111_1111_1111".
|
|
O"777" -- Equivalent to B"111_111_111".
|
|
X"777" -- Equivalent to B"0111_0111_0111".
|
|
B"XXXX_01LH" -- Equivalent to the string literal "XXXX01LH"
|
|
UO"27" -- Equivalent to B"010_111"
|
|
UO"2C" -- Equivalent to B"011_CCC"
|
|
SX"3W" -- Equivalent to B"0011_WWWW"
|
|
D"35" -- Equivalent to B"100011"
|
|
12UB"X1" -- Equivalent to B"0000_0000_00X1"
|
|
12SB"X1" -- Equivalent to B"XXXX_XXXX_XXX1"
|
|
12UX"F-" -- Equivalent to B"0000_1111_----"
|
|
12SX"F-" -- Equivalent to B"1111_1111_----"
|
|
12D"13" -- Equivalent to B"0000_0000_1101"
|
|
12UX"000WWW" -- Equivalent to B"WWWW_WWWW_WWWW"
|
|
12SX"FFFC00" -- Equivalent to B"1100_0000_0000"
|
|
12SX"XXXX00" -- Equivalent to B"XXXX_0000_0000"
|
|
8D"511" -- Error
|
|
8UO"477" -- Error
|
|
8SX"0FF" -- Error
|
|
8SX"FXX" -- Error
|