vasilito
cb424d7448
verify-patch-sanity.py validates every active recipe .patch has internally- consistent hunk line counts — catching the 'malformed patch at line N' failure at commit/CI/preflight time instead of hours into a cook. This cycle hit that class three times (qtwaylandscanner, sddm, xwayland), each only discovered when cookbook tried to apply the patch. Running it across the repo found 29 latent malformed patches (validated against GNU patch: e.g. relibc/P3-sysv-ipc reproduces 'malformed patch at line 22'). They were harmless only because they sit in vendored recipes (baked, not re- applied) — but would fail on any version-bump re-derivation. --fix recounts the hunk headers (body untouched) and repaired all 29. Wired into build-preflight.sh (Phase 1.0D) and redbear-ci.yml, with a unit test (test-patch-sanity.sh). Skips archived/legacy trees and unvalidatable formats (empty placeholders, bare-@@ git hunks).
50 lines
1.7 KiB
C
50 lines
1.7 KiB
C
// RUN: %clang -target mipsel-unknown-linux -S -o - -emit-llvm %s \
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// RUN: | FileCheck %s
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// This checks that the frontend will accept inline asm constraints
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// c', 'l' and 'x'.
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int main(void)
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{
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// 'c': 16 bit address register for Mips16, GPR for all others
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// I am using 'c' to constrain both the target and one of the source
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// registers. We are looking for syntactical correctness.
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// CHECK: %{{[0-9]+}} = call i32 asm sideeffect "addi $0,$1,$2 \0A\09\09", "=c,c,I,~{$1}"(i32 %{{[0-9]+}}, i32 %{{[0-9]+}}) [[NUW:#[0-9]+]], !srcloc !{{[0-9]+}}
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int __s, __v = 17;
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int __t;
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__asm__ __volatile__(
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"addi %0,%1,%2 \n\t\t"
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: "=c" (__t)
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: "c" (__s), "I" (__v));
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// 'l': lo register
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// We are making it clear that destination register is lo with the
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// use of the 'l' constraint ("=l").
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// CHECK: %{{[0-9]+}} = call i32 asm sideeffect "mtlo $1 \0A\09\09", "=l,r,~{lo},~{$1}"(i32 %{{[0-9]+}}) [[NUW]], !srcloc !{{[0-9]+}}
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int i_temp = 44;
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int i_result;
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__asm__ __volatile__(
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"mtlo %1 \n\t\t"
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: "=l" (i_result)
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: "r" (i_temp)
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: "lo");
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// 'x': Combined lo/hi registers
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// We are specifying that destination registers are the hi/lo pair with the
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// use of the 'x' constraint ("=x").
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// CHECK: %{{[0-9]+}} = call i64 asm sideeffect "mthi $1 \0A\09\09mtlo $2 \0A\09\09", "=x,r,r,~{$1}"(i32 %{{[0-9]+}}, i32 %{{[0-9]+}}) [[NUW]], !srcloc !{{[0-9]+}}
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int i_hi = 3;
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int i_lo = 2;
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long long ll_result = 0;
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__asm__ __volatile__(
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"mthi %1 \n\t\t"
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"mtlo %2 \n\t\t"
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: "=x" (ll_result)
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: "r" (i_hi), "r" (i_lo)
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: );
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return 0;
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}
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// CHECK: attributes [[NUW]] = { nounwind }
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