bjorn3
462 lines
18 KiB
Rust
462 lines
18 KiB
Rust
use std::fs::{File, metadata, read_dir};
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use std::io::prelude::*;
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use std::os::unix::io::{FromRawFd, RawFd};
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use std::process::Command;
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use std::thread;
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use std::sync::{Arc, Mutex};
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use pci_types::{CommandRegister, PciAddress};
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use structopt::StructOpt;
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use log::{debug, error, info, warn, trace};
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use redox_log::{OutputBuilder, RedoxLogger};
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use crate::cfg_access::Pcie;
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use crate::config::Config;
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use crate::driver_interface::LegacyInterruptLine;
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use crate::pci::PciFunc;
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use crate::pci::cap::Capability as PciCapability;
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use crate::pci::func::{ConfigReader, ConfigWriter};
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use crate::pci_header::{PciEndpointHeader, PciHeader, PciHeaderError};
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mod cfg_access;
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mod config;
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mod driver_interface;
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mod pci;
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mod pci_header;
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#[derive(StructOpt)]
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#[structopt(about)]
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struct Args {
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#[structopt(short, long,
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help="Increase logging level once for each arg.", parse(from_occurrences))]
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verbose: u8,
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#[structopt(
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help="A path to a pcid config file or a directory that contains pcid config files.")]
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config_path: Option<String>,
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}
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pub struct DriverHandler {
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addr: PciAddress,
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capabilities: Vec<(u8, PciCapability)>,
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state: Arc<State>,
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}
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impl DriverHandler {
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fn respond(&mut self, request: driver_interface::PcidClientRequest, args: &driver_interface::SubdriverArguments) -> driver_interface::PcidClientResponse {
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use driver_interface::*;
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use crate::pci::cap::{MsiCapability, MsixCapability};
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let func = PciFunc {
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pci: &self.state.pcie,
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addr: self.addr,
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};
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match request {
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PcidClientRequest::RequestCapabilities => {
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PcidClientResponse::Capabilities(self.capabilities.iter().map(|(_, capability)| capability.clone()).collect::<Vec<_>>())
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}
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PcidClientRequest::RequestConfig => {
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PcidClientResponse::Config(args.clone())
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}
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PcidClientRequest::RequestFeatures => {
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PcidClientResponse::AllFeatures(self.capabilities.iter().filter_map(|(_, capability)| match capability {
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PciCapability::Msi(msi) => Some((PciFeature::Msi, FeatureStatus::enabled(msi.enabled()))),
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PciCapability::MsiX(msix) => Some((PciFeature::MsiX, FeatureStatus::enabled(msix.msix_enabled()))),
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_ => None,
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}).collect())
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}
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PcidClientRequest::EnableFeature(feature) => match feature {
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PciFeature::Msi => {
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let (offset, capability): (u8, &mut MsiCapability) = match self.capabilities.iter_mut().find_map(|&mut (offset, ref mut capability)| capability.as_msi_mut().map(|cap| (offset, cap))) {
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Some(tuple) => tuple,
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None => return PcidClientResponse::Error(PcidServerResponseError::NonexistentFeature(feature)),
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};
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unsafe {
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capability.set_enabled(true);
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capability.write_message_control(&func, offset);
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}
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PcidClientResponse::FeatureEnabled(feature)
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}
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PciFeature::MsiX => {
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let (offset, capability): (u8, &mut MsixCapability) = match self.capabilities.iter_mut().find_map(|&mut (offset, ref mut capability)| capability.as_msix_mut().map(|cap| (offset, cap))) {
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Some(tuple) => tuple,
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None => return PcidClientResponse::Error(PcidServerResponseError::NonexistentFeature(feature)),
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};
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unsafe {
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capability.set_msix_enabled(true);
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capability.write_a(&func, offset);
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}
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PcidClientResponse::FeatureEnabled(feature)
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}
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}
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PcidClientRequest::FeatureStatus(feature) => PcidClientResponse::FeatureStatus(feature, match feature {
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PciFeature::Msi => self.capabilities.iter().find_map(|(_, capability)| if let PciCapability::Msi(msi) = capability {
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Some(FeatureStatus::enabled(msi.enabled()))
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} else {
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None
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}).unwrap_or(FeatureStatus::Disabled),
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PciFeature::MsiX => self.capabilities.iter().find_map(|(_, capability)| if let PciCapability::MsiX(msix) = capability {
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Some(FeatureStatus::enabled(msix.msix_enabled()))
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} else {
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None
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}).unwrap_or(FeatureStatus::Disabled),
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}),
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PcidClientRequest::FeatureInfo(feature) => PcidClientResponse::FeatureInfo(feature, match feature {
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PciFeature::Msi => if let Some(info) = self.capabilities.iter().find_map(|(_, capability)| capability.as_msi()) {
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PciFeatureInfo::Msi(*info)
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} else {
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return PcidClientResponse::Error(PcidServerResponseError::NonexistentFeature(feature));
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}
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PciFeature::MsiX => if let Some(info) = self.capabilities.iter().find_map(|(_, capability)| capability.as_msix()) {
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PciFeatureInfo::MsiX(*info)
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} else {
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return PcidClientResponse::Error(PcidServerResponseError::NonexistentFeature(feature));
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}
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}),
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PcidClientRequest::SetFeatureInfo(info_to_set) => match info_to_set {
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SetFeatureInfo::Msi(info_to_set) => if let Some((offset, info)) = self.capabilities.iter_mut().find_map(|(offset, capability)| Some((*offset, capability.as_msi_mut()?))) {
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if let Some(mme) = info_to_set.multi_message_enable {
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if info.multi_message_capable() < mme || mme > 0b101 {
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return PcidClientResponse::Error(PcidServerResponseError::InvalidBitPattern);
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}
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info.set_multi_message_enable(mme);
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}
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if let Some(message_addr_and_data) = info_to_set.message_address_and_data {
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let message_addr = message_addr_and_data.addr;
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if message_addr & 0b11 != 0 {
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return PcidClientResponse::Error(PcidServerResponseError::InvalidBitPattern);
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}
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info.set_message_address(message_addr as u32);
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info.set_message_upper_address((message_addr >> 32) as u32);
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if message_addr_and_data.data & ((1 << info.multi_message_enable()) - 1) != 0 {
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return PcidClientResponse::Error(PcidServerResponseError::InvalidBitPattern);
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}
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info.set_message_data(
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message_addr_and_data
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.data
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.try_into()
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.expect("pcid: MSI message data too big"),
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);
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}
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if let Some(mask_bits) = info_to_set.mask_bits {
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info.set_mask_bits(mask_bits);
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}
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unsafe {
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info.write_all(&func, offset);
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}
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PcidClientResponse::SetFeatureInfo(PciFeature::Msi)
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} else {
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return PcidClientResponse::Error(PcidServerResponseError::NonexistentFeature(PciFeature::Msi));
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}
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SetFeatureInfo::MsiX { function_mask } => if let Some((offset, info)) = self.capabilities.iter_mut().find_map(|(offset, capability)| Some((*offset, capability.as_msix_mut()?))) {
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if let Some(mask) = function_mask {
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info.set_function_mask(mask);
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unsafe {
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info.write_a(&func, offset);
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}
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}
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PcidClientResponse::SetFeatureInfo(PciFeature::MsiX)
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} else {
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return PcidClientResponse::Error(PcidServerResponseError::NonexistentFeature(PciFeature::MsiX));
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}
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}
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PcidClientRequest::ReadConfig(offset) => {
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let value = unsafe { func.read_u32(offset) };
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return PcidClientResponse::ReadConfig(value);
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},
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PcidClientRequest::WriteConfig(offset, value) => {
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unsafe {
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func.write_u32(offset, value);
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}
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return PcidClientResponse::WriteConfig;
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}
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}
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}
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fn handle_spawn(mut self, pcid_to_client_write: usize, pcid_from_client_read: usize, args: driver_interface::SubdriverArguments) {
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use driver_interface::*;
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let mut pcid_to_client = unsafe { File::from_raw_fd(pcid_to_client_write as RawFd) };
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let mut pcid_from_client = unsafe { File::from_raw_fd(pcid_from_client_read as RawFd) };
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while let Ok(msg) = recv(&mut pcid_from_client) {
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let response = self.respond(msg, &args);
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send(&mut pcid_to_client, &response).unwrap();
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}
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}
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}
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pub struct State {
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threads: Mutex<Vec<thread::JoinHandle<()>>>,
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pcie: Pcie,
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}
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fn handle_parsed_header(state: Arc<State>, config: &Config, header: PciEndpointHeader) {
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for driver in config.drivers.iter() {
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if !driver.match_function(header.full_device_id()) {
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continue;
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}
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let Some(ref args) = driver.command else {
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continue;
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};
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let mut string = String::new();
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let bars = header.bars(&state.pcie);
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for (i, bar) in bars.iter().enumerate() {
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if !bar.is_none() {
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string.push_str(&format!(" {i}={}", bar.display()));
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}
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}
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if !string.is_empty() {
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info!(" BAR{}", string);
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}
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let mut endpoint_header = header.endpoint_header(&state.pcie);
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// Enable bus mastering, memory space, and I/O space
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endpoint_header.update_command(&state.pcie, |cmd| {
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cmd | CommandRegister::BUS_MASTER_ENABLE
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| CommandRegister::MEMORY_ENABLE
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| CommandRegister::IO_ENABLE
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});
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// Set IRQ line to 9 if not set
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let mut irq = 0xFF;
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let mut interrupt_pin = 0xFF;
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endpoint_header.update_interrupt(&state.pcie, |(pin, mut line)| {
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if line == 0xFF {
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line = 9;
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}
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irq = line;
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interrupt_pin = pin;
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(pin, line)
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});
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let legacy_interrupt_enabled = match interrupt_pin {
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0 => false,
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1 | 2 | 3 | 4 => true,
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other => {
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warn!("pcid: invalid interrupt pin: {}", other);
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false
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}
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};
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let capabilities = if endpoint_header.status(&state.pcie).has_capability_list() {
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let func = PciFunc {
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pci: &state.pcie,
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addr: header.address(),
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};
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crate::pci::cap::CapabilitiesIter::new(header.cap_pointer(), &func).collect::<Vec<_>>()
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} else {
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Vec::new()
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};
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debug!("PCI DEVICE CAPABILITIES for {}: {:?}", args.iter().map(|string| string.as_ref()).nth(0).unwrap_or("[unknown]"), capabilities);
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let func = driver_interface::PciFunction {
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bars,
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addr: header.address(),
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legacy_interrupt_line: if legacy_interrupt_enabled {
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Some(LegacyInterruptLine(irq))
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} else {
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None
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},
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full_device_id: header.full_device_id().clone(),
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};
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let subdriver_args = driver_interface::SubdriverArguments {
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func,
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};
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let mut args = args.iter();
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if let Some(program) = args.next() {
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let mut command = Command::new(program);
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for arg in args {
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if arg.starts_with("$") {
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panic!("support for $VARIABLE has been removed. use pcid_interface instead");
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}
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command.arg(arg);
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}
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info!("PCID SPAWN {:?}", command);
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// TODO: libc wrapper?
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let [fds1, fds2] = unsafe {
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let mut fds1 = [0 as libc::c_int; 2];
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let mut fds2 = [0 as libc::c_int; 2];
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assert_eq!(libc::pipe(fds1.as_mut_ptr()), 0, "pcid: failed to create pcid->client pipe");
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assert_eq!(libc::pipe(fds2.as_mut_ptr()), 0, "pcid: failed to create client->pcid pipe");
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[
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fds1.map(|c| c as usize),
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fds2.map(|c| c as usize),
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]
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};
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let [pcid_to_client_read, pcid_to_client_write] = fds1;
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let [pcid_from_client_read, pcid_from_client_write] = fds2;
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let envs = vec![
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("PCID_TO_CLIENT_FD", format!("{}", pcid_to_client_read)),
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("PCID_FROM_CLIENT_FD", format!("{}", pcid_from_client_write)),
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];
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match command.envs(envs).spawn() {
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Ok(mut child) => {
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let driver_handler = DriverHandler {
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addr: header.address(),
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state: Arc::clone(&state),
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capabilities,
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};
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let _handle = thread::spawn(move || {
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driver_handler.handle_spawn(pcid_to_client_write, pcid_from_client_read, subdriver_args);
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});
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// FIXME this currently deadlocks as pcid doesn't daemonize
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//state.threads.lock().unwrap().push(handle);
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match child.wait() {
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Ok(_status) => (),
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Err(err) => error!("pcid: failed to wait for {:?}: {}", command, err),
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}
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}
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Err(err) => error!("pcid: failed to execute {:?}: {}", command, err)
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}
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}
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}
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}
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fn setup_logging(verbosity: u8) -> Option<&'static RedoxLogger> {
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let log_level = match verbosity {
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0 => log::LevelFilter::Info,
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1 => log::LevelFilter::Debug,
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_ => log::LevelFilter::Trace,
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};
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let mut logger = RedoxLogger::new()
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.with_output(
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OutputBuilder::stderr()
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.with_ansi_escape_codes()
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.with_filter(log_level)
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.flush_on_newline(true)
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.build()
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);
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#[cfg(target_os = "redox")] {
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match OutputBuilder::in_redox_logging_scheme("bus", "pci", "pcid.log") {
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Ok(b) => logger = logger.with_output(
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b.with_filter(log::LevelFilter::Trace)
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.flush_on_newline(true)
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.build()
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),
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Err(error) => eprintln!("pcid: failed to open pcid.log"),
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}
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match OutputBuilder::in_redox_logging_scheme("bus", "pci", "pcid.ansi.log") {
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Ok(b) => logger = logger.with_output(
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b.with_filter(log::LevelFilter::Trace)
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.with_ansi_escape_codes()
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.flush_on_newline(true)
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.build()
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),
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Err(error) => eprintln!("pcid: failed to open pcid.ansi.log"),
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}
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}
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match logger.enable() {
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Ok(logger_ref) => {
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eprintln!("pcid: enabled logger");
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Some(logger_ref)
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}
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Err(error) => {
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eprintln!("pcid: failed to set default logger: {}", error);
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None
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}
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}
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}
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#[paw::main]
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fn main(args: Args) {
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let mut config = Config::default();
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if let Some(config_path) = args.config_path {
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if metadata(&config_path).unwrap().is_file() {
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if let Ok(mut config_file) = File::open(&config_path) {
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let mut config_data = String::new();
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if let Ok(_) = config_file.read_to_string(&mut config_data) {
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config = toml::from_str(&config_data).unwrap_or(Config::default());
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}
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}
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} else {
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let paths = read_dir(&config_path).unwrap();
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let mut config_data = String::new();
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for path in paths {
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if let Ok(mut config_file) = File::open(&path.unwrap().path()) {
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let mut tmp = String::new();
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if let Ok(_) = config_file.read_to_string(&mut tmp) {
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config_data.push_str(&tmp);
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}
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}
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}
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config = toml::from_str(&config_data).unwrap_or(Config::default());
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}
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}
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let _logger_ref = setup_logging(args.verbose);
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let state = Arc::new(State {
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pcie: Pcie::new(),
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threads: Mutex::new(Vec::new()),
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});
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info!("PCI SG-BS:DV.F VEND:DEVI CL.SC.IN.RV");
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// FIXME Use full ACPI for enumerating the host bridges. MCFG only describes the first
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// host bridge, while multi-processor systems likely have a host bridge for each CPU.
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// See also https://www.kernel.org/doc/html/latest/PCI/acpi-info.html
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let mut bus_nums = vec![0];
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let mut bus_i = 0;
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while bus_i < bus_nums.len() {
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let bus_num = bus_nums[bus_i];
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bus_i += 1;
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'dev: for dev_num in 0..32 {
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for func_num in 0..8 {
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let func_addr = PciAddress::new(0, bus_num, dev_num, func_num);
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match PciHeader::from_reader(&state.pcie, func_addr) {
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Ok(header) => {
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info!("{}", header.display());
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match header {
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PciHeader::General(endpoint_header) => {
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handle_parsed_header(Arc::clone(&state), &config, endpoint_header);
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}
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PciHeader::PciToPci {
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secondary_bus_num, ..
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} => {
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bus_nums.push(secondary_bus_num);
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}
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}
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}
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Err(PciHeaderError::NoDevice) => {
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if func_addr.function() == 0 {
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trace!("PCI {:>02X}:{:>02X}: no dev", bus_num, dev_num);
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continue 'dev;
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}
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},
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Err(PciHeaderError::UnknownHeaderType(id)) => {
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warn!("pcid: unknown header type: {id:?}");
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}
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}
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}
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}
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}
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for thread in state.threads.lock().unwrap().drain(..) {
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thread.join().unwrap();
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}
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}
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