Phase G.2 of the ACPI/Arrow Lake port. The LG Gram 2025 (Core Ultra 7
255H, Arrow Lake-H) uses Intel HWP for P-state control — legacy
IA32_PERF_CTL writes are silently ignored when HWP is active.
The previous cpufreqd always wrote IA32_PERF_CTL (MSR 0x199), which
on Arrow Lake-H had zero effect. We now:
1. Detect HWP at startup by reading IA32_PM_ENABLE (MSR 0x770) bit 0
2. If HWP is active:
a. Read IA32_HWP_CAPABILITIES (MSR 0x771) for the
min/max/guaranteed/efficient performance range
b. Translate the governor's P-state index into the HWP
"Desired Performance" field + EPP hint
c. Write IA32_HWP_REQUEST (MSR 0x774) instead of IA32_PERF_CTL
3. If HWP is not active, fall back to the legacy IA32_PERF_CTL path
(preserves backward compatibility for older CPUs)
The kernel's new /scheme/sys/msr/ scheme (Phase G.1) provides the
in-memory storage backing the MSR reads/writes. On the real LG Gram
2025 hardware, the kernel's MSR scheme will be wired to the actual
hardware MSRs (Phase G+ work); the cpufreqd interface is unchanged.
HWP layout (Intel SDM Vol 3B §14.4.4):
[7:0] Minimum Performance
[15:8] Maximum Performance
[23:16] Desired Performance
[31:24] Energy-Performance Preference (EPP)
[42:32] Activity Window (0 = auto)
[42] Package Control
EPP follows the same index as desired perf: 0 = performance,
255 = power-save. We map the linear P-state index to both the
"Desired Performance" and EPP so the H/W sees a single hint that
the OS wants both the performance and energy level it implies.
Includes:
- PstateMode enum (LegacyPerfCtl | Hwp) for compile-time dispatch
- detect_pstate_mode() reads MSR 0x770
- read_hwp_capabilities() reads MSR 0x771, returns (min, max,
guaranteed, efficient) bytes
- hwp_request_for() maps P-state index to IA32_HWP_REQUEST u64
- apply_pstate() dispatches to the right MSR based on ci.mode
- The /scheme/cpufreq/state output now tags each CPU with [HWP] or
[legacy] for observability
Hardware test plan: on the LG Gram 2025, "performance" governor
should pin IA32_HWP_REQUEST.Desired = hwp_max with EPP=0; "powersave"
should pin it to hwp_min with EPP=255; "ondemand" should ramp
between. Reading IA32_PERF_STATUS (MSR 0x198) via /scheme/sys/msr
should reflect the new operating point within ~1ms.
Red Bear OS
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