Cross-referenced with Linux 7.1 xhci-pci.c ZERO_64B_REGS enforcement.
Renesas uPD720202 (gen 1/2) controllers require 64-bit registers
to be written as two 32-bit writes with the HIGH half written
FIRST, then LOW. Normal path writes LOW then HIGH. Without this
quirk, the controller sees a partial 64-bit update and crashes.
Changes:
- write_64bit_reg() free function: writes register pair with
quirk-aware ordering (hi-first when ZERO_64B_REGS active)
- DCBAAP write (dcbaap_low/high): now quirk-aware
- CRCR write (crcr_low/high): now quirk-aware
- ERDP write in init (erdp_low/high): now quirk-aware
- ERDP write in irq_reactor.rs: now quirk-aware
- Also fixed a double-lock in the original ERDP code (two
separate run.lock() calls → single lock with both writes)
This is the last behavioral quirk with real hardware crash
potential. Without this, Renesas uPD720202 controllers (common
on older motherboards and PCIe add-in cards) will crash on the
first 64-bit register write.
Quirk enforcement: 45→46/50 meaningful (92%). Remaining 4 are
umbrella HOST quirks covered by their sub-quirks.
Red Bear OS
1c7f8390b3