bjorn3
480 lines
17 KiB
Rust
480 lines
17 KiB
Rust
use bitflags::bitflags;
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use byteorder::{ByteOrder, LittleEndian};
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use serde::{Deserialize, Serialize};
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use super::bar::PciBar;
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use super::class::PciClass;
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use super::func::ConfigReader;
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#[derive(Debug, PartialEq)]
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pub enum PciHeaderError {
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NoDevice,
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UnknownHeaderType(u8),
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}
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bitflags! {
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/// Flags found in the status register of a PCI device
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#[derive(Serialize, Deserialize)]
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pub struct PciHeaderType: u8 {
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/// A general PCI device (Type 0x01).
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const GENERAL = 0b00000000;
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/// A PCI-to-PCI bridge device (Type 0x01).
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const PCITOPCI = 0b00000001;
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/// A PCI-to-PCI bridge device (Type 0x02).
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const CARDBUSBRIDGE = 0b00000010;
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/// A multifunction device.
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const MULTIFUNCTION = 0b01000000;
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/// Mask used for fetching the header type.
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const HEADER_TYPE = 0b00000011;
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}
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}
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#[derive(Clone, Copy, Debug, PartialEq, Serialize, Deserialize)]
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pub struct SharedPciHeader {
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vendor_id: u16,
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device_id: u16,
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command: u16,
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status: u16,
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revision: u8,
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interface: u8,
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subclass: u8,
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class: PciClass,
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cache_line_size: u8,
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latency_timer: u8,
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header_type: PciHeaderType,
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bist: u8,
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}
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#[derive(Clone, Copy, Debug, PartialEq, Serialize, Deserialize)]
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pub enum PciHeader {
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General {
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shared: SharedPciHeader,
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bars: [PciBar; 6],
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cardbus_cis_ptr: u32,
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subsystem_vendor_id: u16,
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subsystem_id: u16,
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expansion_rom_bar: u32,
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cap_pointer: u8,
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interrupt_line: u8,
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interrupt_pin: u8,
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min_grant: u8,
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max_latency: u8,
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},
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PciToPci {
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shared: SharedPciHeader,
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bars: [PciBar; 2],
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primary_bus_num: u8,
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secondary_bus_num: u8,
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subordinate_bus_num: u8,
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secondary_latency_timer: u8,
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io_base: u8,
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io_limit: u8,
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secondary_status: u16,
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mem_base: u16,
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mem_limit: u16,
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prefetch_base: u16,
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prefetch_limit: u16,
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prefetch_base_upper: u32,
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prefetch_limit_upper: u32,
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io_base_upper: u16,
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io_limit_upper: u16,
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cap_pointer: u8,
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expansion_rom: u32,
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interrupt_line: u8,
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interrupt_pin: u8,
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bridge_control: u16,
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},
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}
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impl PciHeader {
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fn get_bars(bytes: &[u8], bars: &mut [PciBar]) {
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let mut i = 0;
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while i < bars.len() {
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let offset = i * 4;
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let bar_bytes = match bytes.get(offset..offset + 4) {
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Some(some) => some,
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None => continue,
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};
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match PciBar::from(LittleEndian::read_u32(bar_bytes)) {
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PciBar::Memory64(mut addr) => {
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let high_bytes = match bytes.get(offset + 4..offset + 8) {
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Some(some) => some,
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None => continue,
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};
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addr |= (LittleEndian::read_u32(high_bytes) as u64) << 32;
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bars[i] = PciBar::Memory64(addr);
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i += 2;
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}
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bar => {
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bars[i] = bar;
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i += 1;
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}
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}
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}
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}
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/// Parse the bytes found in the Configuration Space of the PCI device into
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/// a more usable PciHeader.
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pub fn from_reader<T: ConfigReader>(reader: T) -> Result<PciHeader, PciHeaderError> {
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if unsafe { reader.read_u32(0) } != 0xffffffff {
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// Read the initial 16 bytes and set variables used by all header types.
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let bytes = unsafe { reader.read_range(0, 16) };
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let vendor_id = LittleEndian::read_u16(&bytes[0..2]);
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let device_id = LittleEndian::read_u16(&bytes[2..4]);
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let command = LittleEndian::read_u16(&bytes[4..6]);
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let status = LittleEndian::read_u16(&bytes[6..8]);
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let revision = bytes[8];
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let interface = bytes[9];
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let subclass = bytes[10];
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let class = PciClass::from(bytes[11]);
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let cache_line_size = bytes[12];
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let latency_timer = bytes[13];
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let header_type = PciHeaderType::from_bits_truncate(bytes[14]);
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let bist = bytes[15];
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let shared = SharedPciHeader {
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vendor_id,
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device_id,
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command,
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status,
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revision,
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interface,
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subclass,
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class,
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cache_line_size,
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latency_timer,
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header_type,
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bist,
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};
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match header_type & PciHeaderType::HEADER_TYPE {
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PciHeaderType::GENERAL => {
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let bytes = unsafe { reader.read_range(16, 48) };
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let mut bars = [PciBar::None; 6];
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Self::get_bars(&bytes, &mut bars);
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let cardbus_cis_ptr = LittleEndian::read_u32(&bytes[24..28]);
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let subsystem_vendor_id = LittleEndian::read_u16(&bytes[28..30]);
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let subsystem_id = LittleEndian::read_u16(&bytes[30..32]);
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let expansion_rom_bar = LittleEndian::read_u32(&bytes[32..36]);
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let cap_pointer = bytes[36];
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let interrupt_line = bytes[44];
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let interrupt_pin = bytes[45];
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let min_grant = bytes[46];
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let max_latency = bytes[47];
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Ok(PciHeader::General {
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shared,
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bars,
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cardbus_cis_ptr,
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subsystem_vendor_id,
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subsystem_id,
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expansion_rom_bar,
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cap_pointer,
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interrupt_line,
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interrupt_pin,
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min_grant,
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max_latency,
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})
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}
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PciHeaderType::PCITOPCI => {
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let bytes = unsafe { reader.read_range(16, 48) };
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let mut bars = [PciBar::None; 2];
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Self::get_bars(&bytes, &mut bars);
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let primary_bus_num = bytes[8];
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let secondary_bus_num = bytes[9];
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let subordinate_bus_num = bytes[10];
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let secondary_latency_timer = bytes[11];
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let io_base = bytes[12];
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let io_limit = bytes[13];
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let secondary_status = LittleEndian::read_u16(&bytes[14..16]);
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let mem_base = LittleEndian::read_u16(&bytes[16..18]);
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let mem_limit = LittleEndian::read_u16(&bytes[18..20]);
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let prefetch_base = LittleEndian::read_u16(&bytes[20..22]);
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let prefetch_limit = LittleEndian::read_u16(&bytes[22..24]);
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let prefetch_base_upper = LittleEndian::read_u32(&bytes[24..28]);
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let prefetch_limit_upper = LittleEndian::read_u32(&bytes[28..32]);
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let io_base_upper = LittleEndian::read_u16(&bytes[32..34]);
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let io_limit_upper = LittleEndian::read_u16(&bytes[34..36]);
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let cap_pointer = bytes[36];
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let expansion_rom = LittleEndian::read_u32(&bytes[40..44]);
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let interrupt_line = bytes[44];
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let interrupt_pin = bytes[45];
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let bridge_control = LittleEndian::read_u16(&bytes[46..48]);
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Ok(PciHeader::PciToPci {
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shared,
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bars,
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primary_bus_num,
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secondary_bus_num,
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subordinate_bus_num,
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secondary_latency_timer,
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io_base,
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io_limit,
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secondary_status,
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mem_base,
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mem_limit,
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prefetch_base,
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prefetch_limit,
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prefetch_base_upper,
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prefetch_limit_upper,
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io_base_upper,
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io_limit_upper,
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cap_pointer,
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expansion_rom,
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interrupt_line,
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interrupt_pin,
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bridge_control,
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})
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}
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id => Err(PciHeaderError::UnknownHeaderType(id.bits())),
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}
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} else {
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Err(PciHeaderError::NoDevice)
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}
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}
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/// Return the Header Type.
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pub fn header_type(&self) -> PciHeaderType {
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match self {
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&PciHeader::General {
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shared: SharedPciHeader { header_type, .. },
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..
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}
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| &PciHeader::PciToPci {
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shared: SharedPciHeader { header_type, .. },
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..
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} => header_type,
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}
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}
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/// Return the Vendor ID field.
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pub fn vendor_id(&self) -> u16 {
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match self {
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&PciHeader::General {
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shared: SharedPciHeader { vendor_id, .. },
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..
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}
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| &PciHeader::PciToPci {
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shared: SharedPciHeader { vendor_id, .. },
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..
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} => vendor_id,
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}
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}
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/// Return the Device ID field.
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pub fn device_id(&self) -> u16 {
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match self {
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&PciHeader::General {
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shared: SharedPciHeader { device_id, .. },
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..
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}
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| &PciHeader::PciToPci {
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shared: SharedPciHeader { device_id, .. },
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..
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} => device_id,
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}
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}
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/// Return the Revision field.
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pub fn revision(&self) -> u8 {
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match self {
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&PciHeader::General {
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shared: SharedPciHeader { revision, .. },
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..
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}
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| &PciHeader::PciToPci {
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shared: SharedPciHeader { revision, .. },
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..
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} => revision,
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}
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}
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/// Return the Interface field.
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pub fn interface(&self) -> u8 {
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match self {
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&PciHeader::General {
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shared: SharedPciHeader { interface, .. },
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..
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}
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| &PciHeader::PciToPci {
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shared: SharedPciHeader { interface, .. },
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..
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} => interface,
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}
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}
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/// Return the Subclass field.
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pub fn subclass(&self) -> u8 {
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match self {
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&PciHeader::General {
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shared: SharedPciHeader { subclass, .. },
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..
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}
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| &PciHeader::PciToPci {
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shared: SharedPciHeader { subclass, .. },
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..
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} => subclass,
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}
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}
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/// Return the Class field.
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pub fn class(&self) -> PciClass {
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match self {
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&PciHeader::General {
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shared: SharedPciHeader { class, .. },
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..
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}
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| &PciHeader::PciToPci {
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shared: SharedPciHeader { class, .. },
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..
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} => class,
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}
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}
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/// Return the Headers BARs.
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pub fn bars(&self) -> &[PciBar] {
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match self {
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&PciHeader::General { ref bars, .. } => bars,
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&PciHeader::PciToPci { ref bars, .. } => bars,
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}
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}
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/// Return the BAR at the given index.
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///
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/// # Panics
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/// This function panics if the requested BAR index is beyond the length of the header
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/// types BAR array.
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pub fn get_bar(&self, idx: usize) -> PciBar {
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match self {
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&PciHeader::General { bars, .. } => {
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assert!(idx < 6, "the general PCI device only has 6 BARs");
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bars[idx]
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}
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&PciHeader::PciToPci { bars, .. } => {
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assert!(idx < 2, "the general PCI device only has 2 BARs");
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bars[idx]
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}
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}
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}
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/// Return the Interrupt Line field.
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pub fn interrupt_line(&self) -> u8 {
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match self {
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&PciHeader::General { interrupt_line, .. }
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| &PciHeader::PciToPci { interrupt_line, .. } => interrupt_line,
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}
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}
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pub fn status(&self) -> u16 {
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match self {
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&PciHeader::General {
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shared: SharedPciHeader { status, .. },
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..
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}
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| &PciHeader::PciToPci {
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shared: SharedPciHeader { status, .. },
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..
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} => status,
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}
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}
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pub fn cap_pointer(&self) -> u8 {
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match self {
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&PciHeader::General { cap_pointer, .. } | &PciHeader::PciToPci { cap_pointer, .. } => {
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cap_pointer
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}
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}
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}
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}
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#[cfg(test)]
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impl<'a> ConfigReader for &'a [u8] {
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unsafe fn read_u32(&self, offset: u16) -> u32 {
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let offset = offset as usize;
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assert!(offset < self.len());
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LittleEndian::read_u32(&self[offset..offset + 4])
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}
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}
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#[cfg(test)]
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mod test {
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use super::{PciHeaderError, PciHeader, PciHeaderType};
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use super::super::func::ConfigReader;
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use super::super::class::PciClass;
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use super::super::bar::PciBar;
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const IGB_DEV_BYTES: [u8; 256] = [
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0x86, 0x80, 0x33, 0x15, 0x07, 0x04, 0x10, 0x00, 0x03, 0x00, 0x00, 0x02, 0x10, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x50, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x01, 0xb0, 0x00, 0x00, 0x00, 0x00, 0x58, 0xf7,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd9, 0x15, 0x33, 0x15,
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0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x01, 0x00, 0x00,
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0x01, 0x50, 0x23, 0xc8, 0x08, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x05, 0x70, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x11, 0xa0, 0x04, 0x80, 0x03, 0x00, 0x00, 0x00, 0x03, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
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0x10, 0x00, 0x02, 0x00, 0xc2, 0x8c, 0x00, 0x10, 0x0f, 0x28, 0x19, 0x00, 0x11, 0x5c, 0x42, 0x00,
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0x42, 0x00, 0x11, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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];
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#[test]
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fn tset_parse_igb_dev() {
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let header = PciHeader::from_reader(&IGB_DEV_BYTES[..]).unwrap();
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assert_eq!(header.header_type(), PciHeaderType::GENERAL);
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assert_eq!(header.device_id(), 0x1533);
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assert_eq!(header.vendor_id(), 0x8086);
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assert_eq!(header.revision(), 3);
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assert_eq!(header.interface(), 0);
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assert_eq!(header.class(), PciClass::Network);
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assert_eq!(header.subclass(), 0);
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assert_eq!(header.bars().len(), 6);
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assert_eq!(header.get_bar(0), PciBar::Memory32(0xf7500000));
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assert_eq!(header.get_bar(1), PciBar::None);
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assert_eq!(header.get_bar(2), PciBar::Port(0xb000));
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assert_eq!(header.get_bar(3), PciBar::Memory32(0xf7580000));
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assert_eq!(header.get_bar(4), PciBar::None);
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assert_eq!(header.get_bar(5), PciBar::None);
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assert_eq!(header.interrupt_line(), 10);
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}
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#[test]
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fn test_parse_nonexistent() {
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let bytes = [
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0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff
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];
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assert_eq!(PciHeader::from_reader(&bytes[..]), Err(PciHeaderError::NoDevice));
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}
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#[test]
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fn test_read_range() {
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let res = unsafe { (&IGB_DEV_BYTES[..]).read_range(0, 4) };
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assert_eq!(res, &[0x86, 0x80, 0x33, 0x15][..]);
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let res = unsafe { (&IGB_DEV_BYTES[..]).read_range(16, 32) };
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let expected = [
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0x00, 0x00, 0x50, 0xf7, 0x00, 0x00, 0x00, 0x00,
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0x01, 0xb0, 0x00, 0x00, 0x00, 0x00, 0x58, 0xf7,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
0x00, 0x00, 0x00, 0x00, 0xd9, 0x15, 0x33, 0x15
|
|
];
|
|
assert_eq!(res, expected);
|
|
}
|
|
|
|
macro_rules! read_range_should_panic {
|
|
($name:ident, $len:expr) => {
|
|
#[test]
|
|
#[should_panic(expected = "invalid range length")]
|
|
fn $name() {
|
|
let _ = unsafe { (&IGB_DEV_BYTES[..]).read_range(0, $len) };
|
|
}
|
|
}
|
|
}
|
|
|
|
read_range_should_panic!(test_short_len, 2);
|
|
read_range_should_panic!(test_not_mod_4_len, 7);
|
|
}
|