vasilito
cb424d7448
verify-patch-sanity.py validates every active recipe .patch has internally- consistent hunk line counts — catching the 'malformed patch at line N' failure at commit/CI/preflight time instead of hours into a cook. This cycle hit that class three times (qtwaylandscanner, sddm, xwayland), each only discovered when cookbook tried to apply the patch. Running it across the repo found 29 latent malformed patches (validated against GNU patch: e.g. relibc/P3-sysv-ipc reproduces 'malformed patch at line 22'). They were harmless only because they sit in vendored recipes (baked, not re- applied) — but would fail on any version-bump re-derivation. --fix recounts the hunk headers (body untouched) and repaired all 29. Wired into build-preflight.sh (Phase 1.0D) and redbear-ci.yml, with a unit test (test-patch-sanity.sh). Skips archived/legacy trees and unvalidatable formats (empty placeholders, bare-@@ git hunks).
81 lines
1.6 KiB
TableGen
81 lines
1.6 KiB
TableGen
// RUN: llvm-tblgen -gen-register-info -register-info-debug -I %p/../../include %s -o /dev/null 2>&1 | FileCheck %s
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include "llvm/Target/Target.td"
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def TestTarget : Target;
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def lo : SubRegIndex<32, 0>;
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def hi : SubRegIndex<32, 32>;
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// One superreg with two subregs.
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def Alo : Register<"">;
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def Ahi : Register<"">;
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def A : Register<""> {
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let SubRegs = [Alo, Ahi];
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let SubRegIndices = [lo, hi];
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}
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// Same but the subregs alias.
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def Blo : Register<"">;
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def Bhi : Register<""> {
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let Aliases = [Blo];
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}
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def B : Register<""> {
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let SubRegs = [Blo, Bhi];
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let SubRegIndices = [lo, hi];
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}
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// Same but the superreg has an alias.
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def Clo : Register<"">;
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def Chi : Register<"">;
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def D : Register<"">;
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def C : Register<""> {
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let SubRegs = [Clo, Chi];
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let SubRegIndices = [lo, hi];
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let Aliases = [D];
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}
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def TestRC : RegisterClass<"Test", [i64], 0, (add A, B)>;
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// CHECK-LABEL: Register A:
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// CHECK: SubReg hi = Ahi
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// CHECK: SubReg lo = Alo
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// CHECK: RegUnit 0
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// CHECK: RegUnit 1
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// CHECK-LABEL: Register Ahi:
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// CHECK: RegUnit 1
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// CHECK-LABEL: Register Alo:
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// CHECK: RegUnit 0
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// CHECK-LABEL: Register B:
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// CHECK: SubReg hi = Bhi
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// CHECK: SubReg lo = Blo
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// CHECK: RegUnit 2
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// CHECK: RegUnit 3
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// CHECK: RegUnit 4
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// CHECK-LABEL: Register Bhi:
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// CHECK: RegUnit 3
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// CHECK: RegUnit 4
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// CHECK-LABEL: Register Blo:
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// CHECK: RegUnit 2
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// CHECK: RegUnit 3
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// CHECK-LABEL: Register C:
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// CHECK: SubReg hi = Chi
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// CHECK: SubReg lo = Clo
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// CHECK: RegUnit 5
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// CHECK: RegUnit 6
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// CHECK: RegUnit 7
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// CHECK-LABEL: Register Chi:
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// CHECK: RegUnit 6
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// CHECK-LABEL: Register Clo:
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// CHECK: RegUnit 5
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// CHECK-LABEL: Register D:
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// CHECK: RegUnit 7
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// CHECK: RegUnit 8
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