vasilito
cb424d7448
verify-patch-sanity.py validates every active recipe .patch has internally- consistent hunk line counts — catching the 'malformed patch at line N' failure at commit/CI/preflight time instead of hours into a cook. This cycle hit that class three times (qtwaylandscanner, sddm, xwayland), each only discovered when cookbook tried to apply the patch. Running it across the repo found 29 latent malformed patches (validated against GNU patch: e.g. relibc/P3-sysv-ipc reproduces 'malformed patch at line 22'). They were harmless only because they sit in vendored recipes (baked, not re- applied) — but would fail on any version-bump re-derivation. --fix recounts the hunk headers (body untouched) and repaired all 29. Wired into build-preflight.sh (Phase 1.0D) and redbear-ci.yml, with a unit test (test-patch-sanity.sh). Skips archived/legacy trees and unvalidatable formats (empty placeholders, bare-@@ git hunks).
141 lines
6.9 KiB
C++
141 lines
6.9 KiB
C++
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
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// RUN: %clang_cc1 -triple nvptx64-nvidia-cuda -emit-llvm \
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// RUN: -fvisibility=hidden -o - %s | FileCheck %s --check-prefix=NVPTX
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// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -emit-llvm \
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// RUN: -fvisibility=hidden -o - %s | FileCheck %s --check-prefix=AMDGPU
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// NVPTX-LABEL: define hidden void @_Z1fPv(
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// NVPTX-SAME: ptr noundef [[P:%.*]]) #[[ATTR0:[0-9]+]] {
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// NVPTX-NEXT: [[ENTRY:.*:]]
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// NVPTX-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8
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// NVPTX-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 8
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// NVPTX-NEXT: ret void
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//
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// AMDGPU-LABEL: define hidden void @_Z1fPv(
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// AMDGPU-SAME: ptr noundef [[P:%.*]]) #[[ATTR0:[0-9]+]] {
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// AMDGPU-NEXT: [[ENTRY:.*:]]
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// AMDGPU-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
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// AMDGPU-NEXT: [[P_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[P_ADDR]] to ptr
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// AMDGPU-NEXT: store ptr [[P]], ptr [[P_ADDR_ASCAST]], align 8
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// AMDGPU-NEXT: ret void
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//
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void f(void *p) {}
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// NVPTX-LABEL: define hidden void @_Z2p1Pv(
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// NVPTX-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {
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// NVPTX-NEXT: [[ENTRY:.*:]]
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// NVPTX-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8
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// NVPTX-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 8
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// NVPTX-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR]], align 8
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// NVPTX-NEXT: call void @_Z1fPv(ptr noundef [[TMP0]]) #[[ATTR1:[0-9]+]]
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// NVPTX-NEXT: ret void
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//
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// AMDGPU-LABEL: define hidden void @_Z2p1Pv(
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// AMDGPU-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {
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// AMDGPU-NEXT: [[ENTRY:.*:]]
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// AMDGPU-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
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// AMDGPU-NEXT: [[P_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[P_ADDR]] to ptr
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// AMDGPU-NEXT: store ptr [[P]], ptr [[P_ADDR_ASCAST]], align 8
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// AMDGPU-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR_ASCAST]], align 8
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// AMDGPU-NEXT: call void @_Z1fPv(ptr noundef [[TMP0]]) #[[ATTR1:[0-9]+]]
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// AMDGPU-NEXT: ret void
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//
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void p1(void [[clang::address_space(0)]] * p) { f(p); }
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// NVPTX-LABEL: define hidden noundef ptr @_Z2p2PU3AS3v(
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// NVPTX-SAME: ptr addrspace(3) noundef [[P:%.*]]) #[[ATTR0]] {
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// NVPTX-NEXT: [[ENTRY:.*:]]
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// NVPTX-NEXT: [[P_ADDR:%.*]] = alloca ptr addrspace(3), align 8
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// NVPTX-NEXT: store ptr addrspace(3) [[P]], ptr [[P_ADDR]], align 8
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// NVPTX-NEXT: [[TMP0:%.*]] = load ptr addrspace(3), ptr [[P_ADDR]], align 8
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// NVPTX-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(3) [[TMP0]] to ptr
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// NVPTX-NEXT: ret ptr [[TMP1]]
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//
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// AMDGPU-LABEL: define hidden noundef ptr @_Z2p2PU3AS3v(
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// AMDGPU-SAME: ptr addrspace(3) noundef [[P:%.*]]) #[[ATTR0]] {
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// AMDGPU-NEXT: [[ENTRY:.*:]]
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// AMDGPU-NEXT: [[RETVAL:%.*]] = alloca ptr, align 8, addrspace(5)
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// AMDGPU-NEXT: [[P_ADDR:%.*]] = alloca ptr addrspace(3), align 4, addrspace(5)
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// AMDGPU-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr
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// AMDGPU-NEXT: [[P_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[P_ADDR]] to ptr
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// AMDGPU-NEXT: store ptr addrspace(3) [[P]], ptr [[P_ADDR_ASCAST]], align 4
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// AMDGPU-NEXT: [[TMP0:%.*]] = load ptr addrspace(3), ptr [[P_ADDR_ASCAST]], align 4
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// AMDGPU-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(3) [[TMP0]] to ptr
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// AMDGPU-NEXT: ret ptr [[TMP1]]
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//
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void *p2(void [[clang::address_space(3)]] * p) { return p; }
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// NVPTX-LABEL: define hidden noundef ptr @_Z2p3PU3AS3v(
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// NVPTX-SAME: ptr addrspace(3) noundef [[P:%.*]]) #[[ATTR0]] {
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// NVPTX-NEXT: [[ENTRY:.*:]]
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// NVPTX-NEXT: [[P_ADDR:%.*]] = alloca ptr addrspace(3), align 8
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// NVPTX-NEXT: store ptr addrspace(3) [[P]], ptr [[P_ADDR]], align 8
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// NVPTX-NEXT: [[TMP0:%.*]] = load ptr addrspace(3), ptr [[P_ADDR]], align 8
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// NVPTX-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(3) [[TMP0]] to ptr
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// NVPTX-NEXT: ret ptr [[TMP1]]
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//
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// AMDGPU-LABEL: define hidden noundef ptr @_Z2p3PU3AS3v(
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// AMDGPU-SAME: ptr addrspace(3) noundef [[P:%.*]]) #[[ATTR0]] {
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// AMDGPU-NEXT: [[ENTRY:.*:]]
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// AMDGPU-NEXT: [[RETVAL:%.*]] = alloca ptr, align 8, addrspace(5)
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// AMDGPU-NEXT: [[P_ADDR:%.*]] = alloca ptr addrspace(3), align 4, addrspace(5)
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// AMDGPU-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr
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// AMDGPU-NEXT: [[P_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[P_ADDR]] to ptr
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// AMDGPU-NEXT: store ptr addrspace(3) [[P]], ptr [[P_ADDR_ASCAST]], align 4
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// AMDGPU-NEXT: [[TMP0:%.*]] = load ptr addrspace(3), ptr [[P_ADDR_ASCAST]], align 4
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// AMDGPU-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(3) [[TMP0]] to ptr
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// AMDGPU-NEXT: ret ptr [[TMP1]]
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//
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void *p3(void [[clang::address_space(3)]] * p) { return p; }
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struct S {
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S() = default;
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~S() = default;
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void foo() {}
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};
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S s1;
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S [[clang::address_space(1)]] s2;
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S [[clang::address_space(3)]] s3;
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template <typename Ty> void foo(Ty *) {}
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// NVPTX-LABEL: define hidden void @_Z2t1Pv(
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// NVPTX-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {
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// NVPTX-NEXT: [[ENTRY:.*:]]
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// NVPTX-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8
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// NVPTX-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 8
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// NVPTX-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR]], align 8
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// NVPTX-NEXT: call void @_Z3fooIvEvPT_(ptr noundef [[TMP0]]) #[[ATTR1]]
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// NVPTX-NEXT: ret void
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//
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// AMDGPU-LABEL: define hidden void @_Z2t1Pv(
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// AMDGPU-SAME: ptr noundef [[P:%.*]]) #[[ATTR0]] {
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// AMDGPU-NEXT: [[ENTRY:.*:]]
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// AMDGPU-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
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// AMDGPU-NEXT: [[P_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[P_ADDR]] to ptr
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// AMDGPU-NEXT: store ptr [[P]], ptr [[P_ADDR_ASCAST]], align 8
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// AMDGPU-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR_ASCAST]], align 8
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// AMDGPU-NEXT: call void @_Z3fooIvEvPT_(ptr noundef [[TMP0]]) #[[ATTR1]]
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// AMDGPU-NEXT: ret void
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//
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void t1(void *p) { foo(p); }
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// NVPTX-LABEL: define hidden void @_Z2t3PU3AS3v(
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// NVPTX-SAME: ptr addrspace(3) noundef [[P:%.*]]) #[[ATTR0]] {
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// NVPTX-NEXT: [[ENTRY:.*:]]
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// NVPTX-NEXT: [[P_ADDR:%.*]] = alloca ptr addrspace(3), align 8
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// NVPTX-NEXT: store ptr addrspace(3) [[P]], ptr [[P_ADDR]], align 8
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// NVPTX-NEXT: [[TMP0:%.*]] = load ptr addrspace(3), ptr [[P_ADDR]], align 8
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// NVPTX-NEXT: call void @_Z3fooIU3AS3vEvPT_(ptr addrspace(3) noundef [[TMP0]]) #[[ATTR1]]
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// NVPTX-NEXT: ret void
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//
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// AMDGPU-LABEL: define hidden void @_Z2t3PU3AS3v(
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// AMDGPU-SAME: ptr addrspace(3) noundef [[P:%.*]]) #[[ATTR0]] {
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// AMDGPU-NEXT: [[ENTRY:.*:]]
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// AMDGPU-NEXT: [[P_ADDR:%.*]] = alloca ptr addrspace(3), align 4, addrspace(5)
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// AMDGPU-NEXT: [[P_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[P_ADDR]] to ptr
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// AMDGPU-NEXT: store ptr addrspace(3) [[P]], ptr [[P_ADDR_ASCAST]], align 4
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// AMDGPU-NEXT: [[TMP0:%.*]] = load ptr addrspace(3), ptr [[P_ADDR_ASCAST]], align 4
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// AMDGPU-NEXT: call void @_Z3fooIU3AS3vEvPT_(ptr addrspace(3) noundef [[TMP0]]) #[[ATTR1]]
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// AMDGPU-NEXT: ret void
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//
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void t3(void [[clang::address_space(3)]] *p) { foo(p); }
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