vasilito
cb424d7448
verify-patch-sanity.py validates every active recipe .patch has internally- consistent hunk line counts — catching the 'malformed patch at line N' failure at commit/CI/preflight time instead of hours into a cook. This cycle hit that class three times (qtwaylandscanner, sddm, xwayland), each only discovered when cookbook tried to apply the patch. Running it across the repo found 29 latent malformed patches (validated against GNU patch: e.g. relibc/P3-sysv-ipc reproduces 'malformed patch at line 22'). They were harmless only because they sit in vendored recipes (baked, not re- applied) — but would fail on any version-bump re-derivation. --fix recounts the hunk headers (body untouched) and repaired all 29. Wired into build-preflight.sh (Phase 1.0D) and redbear-ci.yml, with a unit test (test-patch-sanity.sh). Skips archived/legacy trees and unvalidatable formats (empty placeholders, bare-@@ git hunks).
43 lines
1.7 KiB
C
43 lines
1.7 KiB
C
// RUN: %clang_cc1 -triple sparc-unknown-unknown -emit-llvm %s -o - | FileCheck %s
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// CHECK: define{{.*}} float @fabsf(float noundef %a)
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// CHECK: %{{.*}} = call float asm sideeffect "fabss $1, $0;", "=e,f"(float %{{.*}})
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float fabsf(float a) {
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float res;
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__asm __volatile__("fabss %1, %0;"
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: /* reg out*/ "=e"(res)
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: /* reg in */ "f"(a));
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return res;
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}
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void test_gcc_registers(void) {
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register unsigned int regO6 asm("o6") = 0;
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register unsigned int regSP asm("sp") = 1;
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register unsigned int reg14 asm("r14") = 2;
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register unsigned int regI6 asm("i6") = 3;
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register unsigned int regFP asm("fp") = 4;
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register unsigned int reg30 asm("r30") = 5;
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register float fF20 asm("f20") = 8.0;
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register double dF20 asm("f20") = 11.0;
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register long double qF20 asm("f20") = 14.0;
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// Test remapping register names in register ... asm("rN") statments.
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// CHECK: call void asm sideeffect "add $0,$1,$2", "{r14},{r14},{r14}"
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asm volatile("add %0,%1,%2" : : "r" (regO6), "r" (regSP), "r" (reg14));
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// CHECK: call void asm sideeffect "add $0,$1,$2", "{r30},{r30},{r30}"
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asm volatile("add %0,%1,%2" : : "r" (regI6), "r" (regFP), "r" (reg30));
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// CHECK: call void asm sideeffect "fadds $0,$1,$2", "{f20},{f20},{f20}"
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asm volatile("fadds %0,%1,%2" : : "f" (fF20), "f" (fF20), "f"(fF20));
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// CHECK: call void asm sideeffect "faddd $0,$1,$2", "{f20},{f20},{f20}"
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asm volatile("faddd %0,%1,%2" : : "f" (dF20), "f" (dF20), "f"(dF20));
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// CHECK: call void asm sideeffect "faddq $0,$1,$2", "{f20},{f20},{f20}"
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asm volatile("faddq %0,%1,%2" : : "f" (qF20), "f" (qF20), "f"(qF20));
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}
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