vasilito
cee25393d8
- Fix P15-8-init-cycle-detection.patch: replace visiting+error with seen+silent-skip to eliminate 11 false-positive 'dependency cycle detected' errors on shared deps - Fix P0-daemon-fix-init-notify-unwrap.patch: remove eprintln! for missing INIT_NOTIFY (expected for oneshot_async services, ~7 daemons affected) - Fix driver-manager hotplug loop: add PERMANENTLY_SKIPPED static set shared between hotplug handler and DriverConfig::probe() to stop infinite re-probing of Fatal/NotSupported/deferred-exhausted device+driver pairs (e.g. ided) - Fix driver-manager log_timeline: suppress repeated EPIPE/ENOENT errors with AtomicI32 dedup and AtomicBool one-shot guards for boot timeline JSON - Add driver-manager SIGTERM handler, ACPI bus registration, --status mode, driver reap loop, graceful shutdown, and reduced deferred retries (30→3)
181 lines
7.0 KiB
Diff
181 lines
7.0 KiB
Diff
diff --git a/src/context/arch/aarch64.rs b/src/context/arch/aarch64.rs
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index 33dc83a..b8f8ac9 100644
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--- a/src/context/arch/aarch64.rs
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+++ b/src/context/arch/aarch64.rs
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@@ -4,16 +4,10 @@ use crate::{
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percpu::PercpuBlock,
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syscall::FloatRegisters,
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};
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-use core::{mem::offset_of, ptr, sync::atomic::AtomicBool};
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+use core::{mem::offset_of, ptr};
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use spin::Once;
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use syscall::{EnvRegisters, Result};
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-/// This must be used by the kernel to ensure that context switches are done atomically
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-/// Compare and exchange this to true when beginning a context switch on any CPU
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-/// The `Context::switch_to` function will set it back to false, allowing other CPU's to switch
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-/// This must be done, as no locks can be held on the stack during switch
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-pub static CONTEXT_SWITCH_LOCK: AtomicBool = AtomicBool::new(false);
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-
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// 512 bytes for registers, extra bytes for fpcr and fpsr
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pub const KFX_ALIGN: usize = 16;
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diff --git a/src/context/arch/riscv64.rs b/src/context/arch/riscv64.rs
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index 4bd843e..fe63639 100644
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--- a/src/context/arch/riscv64.rs
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+++ b/src/context/arch/riscv64.rs
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@@ -2,13 +2,11 @@ use crate::{
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arch::interrupt::InterruptStack, context::context::Kstack, memory::RmmA, percpu::PercpuBlock,
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syscall::FloatRegisters,
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};
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-use core::{mem::offset_of, sync::atomic::AtomicBool};
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+use core::mem::offset_of;
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use rmm::{Arch, VirtualAddress};
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use spin::Once;
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use syscall::{error::*, EnvRegisters};
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-pub static CONTEXT_SWITCH_LOCK: AtomicBool = AtomicBool::new(false);
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-
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pub const KFX_ALIGN: usize = 16;
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#[derive(Clone, Debug, Default)]
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diff --git a/src/context/arch/x86.rs b/src/context/arch/x86.rs
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index 2862d35..dc01f6e 100644
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--- a/src/context/arch/x86.rs
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+++ b/src/context/arch/x86.rs
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@@ -1,4 +1,4 @@
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-use core::{mem::offset_of, sync::atomic::AtomicBool};
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+use core::mem::offset_of;
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use rmm::{Arch, VirtualAddress};
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use spin::Once;
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use syscall::{error::*, EnvRegisters};
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@@ -14,12 +14,6 @@ use crate::{
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syscall::FloatRegisters,
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};
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-/// This must be used by the kernel to ensure that context switches are done atomically
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-/// Compare and exchange this to true when beginning a context switch on any CPU
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-/// The `Context::switch_to` function will set it back to false, allowing other CPU's to switch
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-/// This must be done, as no locks can be held on the stack during switch
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-pub static CONTEXT_SWITCH_LOCK: AtomicBool = AtomicBool::new(false);
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-
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const ST_RESERVED: u128 = 0xFFFF_FFFF_FFFF_0000_0000_0000_0000_0000;
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pub const KFX_ALIGN: usize = 16;
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diff --git a/src/context/arch/x86_64.rs b/src/context/arch/x86_64.rs
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index 6758c9f..574d373 100644
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--- a/src/context/arch/x86_64.rs
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+++ b/src/context/arch/x86_64.rs
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@@ -1,6 +1,5 @@
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use core::{
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ptr::{addr_of, addr_of_mut},
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- sync::atomic::AtomicBool,
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};
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use crate::syscall::FloatRegisters;
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@@ -12,12 +11,6 @@ use spin::Once;
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use syscall::{error::*, EnvRegisters};
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use x86::msr;
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-/// This must be used by the kernel to ensure that context switches are done atomically
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-/// Compare and exchange this to true when beginning a context switch on any CPU
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-/// The `Context::switch_to` function will set it back to false, allowing other CPU's to switch
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-/// This must be done, as no locks can be held on the stack during switch
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-pub static CONTEXT_SWITCH_LOCK: AtomicBool = AtomicBool::new(false);
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-
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const ST_RESERVED: u128 = 0xFFFF_FFFF_FFFF_0000_0000_0000_0000_0000;
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#[cfg(cpu_feature_never = "xsave")]
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diff --git a/src/context/switch.rs b/src/context/switch.rs
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index 86684c8..d509984 100644
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--- a/src/context/switch.rs
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+++ b/src/context/switch.rs
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@@ -15,8 +15,7 @@ use crate::{
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use alloc::{sync::Arc, vec::Vec};
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use core::{
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cell::{Cell, RefCell},
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- hint, mem,
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- sync::atomic::Ordering,
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+ mem,
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};
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use syscall::PtraceFlags;
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@@ -120,7 +119,10 @@ pub unsafe extern "C" fn switch_finish_hook() {
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crate::arch::stop::emergency_reset();
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}
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}
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- arch::CONTEXT_SWITCH_LOCK.store(false, Ordering::SeqCst);
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+ PercpuBlock::current()
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+ .switch_internals
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+ .in_context_switch
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+ .set(false);
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crate::percpu::switch_arch_hook();
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}
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}
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@@ -150,16 +152,15 @@ pub fn switch(token: &mut CleanLockToken) -> SwitchResult {
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//set PIT Interrupt counter to 0, giving each process same amount of PIT ticks
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percpu.switch_internals.pit_ticks.set(0);
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- // Acquire the global lock to ensure exclusive access during context switch and avoid
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- // issues that would be caused by the unsafe operations below
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- // TODO: Better memory orderings?
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- while arch::CONTEXT_SWITCH_LOCK
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- .compare_exchange_weak(false, true, Ordering::SeqCst, Ordering::Relaxed)
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- .is_err()
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- {
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- hint::spin_loop();
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- percpu.maybe_handle_tlb_shootdown();
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- }
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+ // Acquire the per-CPU context switch flag. Each CPU can only be in one context
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+ // switch at a time. The per-context write locks provide cross-CPU safety; this
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+ // flag catches re-entrant switches on the same CPU (a kernel bug).
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+ debug_assert!(
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+ !percpu.switch_internals.in_context_switch.get(),
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+ "context switch re-entry on CPU {}",
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+ percpu.cpu_id
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+ );
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+ percpu.switch_internals.in_context_switch.set(true);
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// Lock the previous context.
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let prev_context_lock = crate::context::current();
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@@ -167,8 +168,8 @@ pub fn switch(token: &mut CleanLockToken) -> SwitchResult {
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let mut prev_context_guard = unsafe { prev_context_lock.write_arc() };
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if !prev_context_guard.is_preemptable() {
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- // Unset global lock
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- arch::CONTEXT_SWITCH_LOCK.store(false, Ordering::SeqCst);
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+ // Unset per-CPU context switch flag
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+ percpu.switch_internals.in_context_switch.set(false);
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// Pretend to have finished switching, so CPU is not idled
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return SwitchResult::Switched;
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@@ -292,8 +293,8 @@ pub fn switch(token: &mut CleanLockToken) -> SwitchResult {
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SwitchResult::Switched
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}
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_ => {
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- // No target was found, unset global lock and return
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- arch::CONTEXT_SWITCH_LOCK.store(false, Ordering::SeqCst);
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+ // No target was found, unset per-CPU context switch flag and return
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+ percpu.switch_internals.in_context_switch.set(false);
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percpu.stats.set_state(cpu_stats::CpuState::Idle);
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@@ -494,6 +495,9 @@ pub struct ContextSwitchPercpu {
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switch_result: Cell<Option<SwitchResultInner>>,
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switch_time: Cell<u128>,
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pit_ticks: Cell<usize>,
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+ /// Per-CPU context switch flag. Set to true during a context switch on this CPU.
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+ /// Replaced the global CONTEXT_SWITCH_LOCK to eliminate cross-CPU serialization.
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+ in_context_switch: Cell<bool>,
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current_ctxt: RefCell<Option<Arc<ContextLock>>>,
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@@ -508,6 +512,7 @@ impl ContextSwitchPercpu {
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switch_result: Cell::new(None),
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switch_time: Cell::new(0),
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pit_ticks: Cell::new(0),
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+ in_context_switch: Cell::new(false),
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current_ctxt: RefCell::new(None),
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idle_ctxt: RefCell::new(None),
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being_sigkilled: Cell::new(false),
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