vasilito
ba5e010bb7
P21: Replace 67 panic-grade calls across 9 boot daemon files with graceful error handling. Affected: ps2d, inputd, fbcond, fbbootlogd. P22: Add x2APIC MADT fallback for processors with LocalApic entries instead of LocalX2Apic entries. QEMU KVM boots now correctly detect all vCPUs via zero-extended APIC ID fallback. P23: Change 50_rootfs.service from requires_weak to requires on 40_drivers.target, ensuring redoxfs waits for disk drivers before attempting filesystem mount. This fixes the boot race where rootfs mount failed before drivers were ready, causing init to have no userland services after switchroot.
166 lines
7.5 KiB
Diff
166 lines
7.5 KiB
Diff
diff --git a/src/acpi/madt/arch/x86.rs b/src/acpi/madt/arch/x86.rs
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index 306ec154..983fc409 100644
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--- a/src/acpi/madt/arch/x86.rs
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+++ b/src/acpi/madt/arch/x86.rs
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@@ -187,0 +188,10 @@ pub(super) fn init(madt: Madt) {
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+ // Detect whether MADT contains any LocalX2Apic entries.
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+ // Some firmware (notably QEMU and some older BIOS) provides only 8-bit
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+ // LocalApic entries even when the CPU supports x2APIC. In that case we must
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+ // fall back to processing LocalApic entries with zero-extended IDs.
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+ let has_x2apic_entries = madt.iter().any(|e| matches!(e, MadtEntry::LocalX2Apic(_)));
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+ let x2apic_fallback = local_apic.x2 && !has_x2apic_entries;
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+ if x2apic_fallback {
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+ warn!("MADT: x2APIC mode active but no LocalX2Apic entries found; falling back to LocalApic entries with zero-extended IDs");
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+ }
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+
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@@ -196,0 +207,3 @@ pub(super) fn init(madt: Madt) {
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+ MadtEntry::LocalApic(local) if local_apic.x2 && x2apic_fallback => {
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+ u32::from(local.id) == me.get() || local.flags & 1 == 1
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+ }
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@@ -225,2 +238,6 @@ pub(super) fn init(madt: Madt) {
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- // x2APIC mode: skip 8-bit LocalApic IDs; they conflict with
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- // 32-bit x2APIC IDs. Dedup only among LocalX2Apic entries.
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+ if x2apic_fallback {
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+ let id = u32::from(local.id);
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+ if !seen_apic_ids.insert(id) {
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+ warn!("MADT: duplicate APIC ID {} in LocalApic entry (x2APIC fallback), firmware bug", id);
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+ }
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+ } else {
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@@ -228,0 +246 @@ pub(super) fn init(madt: Madt) {
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+ }
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@@ -252 +270 @@ pub(super) fn init(madt: Madt) {
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- if local_apic.x2 {
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+ if local_apic.x2 && !x2apic_fallback {
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@@ -256,0 +275,131 @@ pub(super) fn init(madt: Madt) {
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+ } else if local_apic.x2 && x2apic_fallback {
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+ let apic_id = u32::from(ap_local_apic.id);
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+ if apic_id == me.get() {
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+ debug!(" This is my local APIC (x2APIC fallback, id={})", apic_id);
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+ } else if ap_local_apic.flags & 1 == 1 {
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+ let alloc = match allocate_p2frame(4) {
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+ Some(frame) => frame,
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+ None => {
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+ println!("KERNEL AP: CPU {} no memory for stack, skipping", apic_id);
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+ continue;
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+ }
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+ };
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+ let stack_start = RmmA::phys_to_virt(alloc.base()).data();
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+ let stack_end = stack_start + (PAGE_SIZE << 4);
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+
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+ let cpu_id = LogicalCpuId::new(crate::CPU_COUNT.fetch_add(1, Ordering::SeqCst));
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+ if cpu_id.get() >= crate::cpu_set::MAX_CPU_COUNT {
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+ println!(
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+ "KERNEL AP: CPU {} exceeds logical CPU limit, skipping",
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+ apic_id
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+ );
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+ continue;
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+ }
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+
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+ let pcr_ptr = crate::arch::gdt::allocate_and_init_pcr(cpu_id, stack_end);
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+ let idt_ptr = crate::arch::idt::allocate_and_init_idt(cpu_id);
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+
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+ let args = KernelArgsAp {
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+ stack_end: stack_end as *mut u8,
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+ cpu_id,
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+ pcr_ptr,
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+ idt_ptr,
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+ };
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+
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+ let ap_ready = (TRAMPOLINE + 8) as *mut u64;
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+ let ap_args_ptr = unsafe { ap_ready.add(1) };
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+ let ap_page_table = unsafe { ap_ready.add(2) };
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+ let ap_code = unsafe { ap_ready.add(3) };
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+
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+ unsafe {
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+ ap_ready.write(0);
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+ ap_args_ptr.write(&args as *const _ as u64);
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+ ap_page_table.write(page_table_physaddr as u64);
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+ #[expect(clippy::fn_to_numeric_cast)]
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+ ap_code.write(kstart_ap as u64);
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+
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+ core::sync::atomic::fence(Ordering::SeqCst);
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+ };
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+ AP_READY.store(false, Ordering::SeqCst);
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+
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+ // Clear APIC Error Status Register before starting AP.
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+ unsafe { local_apic.esr(); }
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+
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+ // Send INIT IPI (Assert) — x2APIC uses 64-bit ICR format.
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+ {
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+ let mut icr = 0x4500u64;
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+ icr |= u64::from(apic_id) << 32;
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+ local_apic.set_icr(icr);
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+ }
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+
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+ // Intel SDM Vol 3A §8.4.4: wait 10ms after INIT deassert
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+ early_udelay(10_000);
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+
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+ // Send START IPI #1
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+ {
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+ let ap_segment = (TRAMPOLINE >> 12) & 0xFF;
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+ let mut icr = 0x0600 | ap_segment as u64;
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+ icr |= u64::from(apic_id) << 32;
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+ local_apic.set_icr(icr);
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+ }
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+
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+ early_udelay(200);
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+
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+ // Send START IPI #2 (recommended for compatibility)
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+ {
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+ let ap_segment = (TRAMPOLINE >> 12) & 0xFF;
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+ let mut icr = 0x0600 | ap_segment as u64;
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+ icr |= u64::from(apic_id) << 32;
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+ local_apic.set_icr(icr);
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+ }
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+
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+ early_udelay(200);
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+
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+ // Check ESR for delivery errors after SIPI sequence.
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+ let esr_val = unsafe { local_apic.esr() };
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+ if esr_val != 0 {
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+ println!(
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+ "KERNEL AP: CPU {} SIPI delivery error (ESR={:#x}), continuing",
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+ apic_id, esr_val
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+ );
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+ }
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+
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+ let mut trampoline_ready = false;
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+ for _ in 0..AP_SPIN_LIMIT {
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+ if unsafe { (*ap_ready.cast::<AtomicU8>()).load(Ordering::SeqCst) } != 0 {
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+ trampoline_ready = true;
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+ break;
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+ }
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+ hint::spin_loop();
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+ }
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+ if !trampoline_ready {
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+ println!("KERNEL AP: CPU {} trampoline timeout, skipping", apic_id);
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+ continue;
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+ }
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+
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+ let mut kernel_ready = false;
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+ for _ in 0..AP_SPIN_LIMIT {
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+ if AP_READY.load(Ordering::SeqCst) {
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+ kernel_ready = true;
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+ break;
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+ }
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+ hint::spin_loop();
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+ }
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+ if !kernel_ready {
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+ println!("KERNEL AP: CPU {} AP_READY timeout, skipping", apic_id);
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+ continue;
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+ }
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+
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+ // Record APIC→CPU mapping for NUMA topology.
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+ unsafe {
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+ record_apic_mapping(apic_id, cpu_id);
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+ }
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+ // Set NUMA node from SRAT data.
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+ if let Some(percpu) = crate::percpu::get_for_cpu(cpu_id) {
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+ if let Some(node) = crate::acpi::srat::numa_node_for_apic(apic_id) {
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+ percpu.numa_node.set(node);
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+ }
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+ }
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+
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+ RmmA::invalidate_all();
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+ }
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