bjorn3
294 lines
9.6 KiB
Rust
294 lines
9.6 KiB
Rust
use std::convert::TryInto;
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use pci_types::{
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Bar as TyBar, ConfigRegionAccess, EndpointHeader, HeaderType, PciAddress,
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PciHeader as TyPciHeader, PciPciBridgeHeader,
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};
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use crate::pci::{FullDeviceId, PciBar};
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#[derive(Debug, PartialEq)]
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pub enum PciHeaderError {
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NoDevice,
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UnknownHeaderType(HeaderType),
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}
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub struct SharedPciHeader {
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full_device_id: FullDeviceId,
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addr: PciAddress,
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}
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub struct PciEndpointHeader {
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shared: SharedPciHeader,
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subsystem_vendor_id: u16,
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subsystem_id: u16,
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cap_pointer: u8,
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}
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum PciHeader {
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General(PciEndpointHeader),
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PciToPci {
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shared: SharedPciHeader,
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secondary_bus_num: u8,
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cap_pointer: u8,
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},
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}
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impl PciHeader {
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/// Parse the bytes found in the Configuration Space of the PCI device into
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/// a more usable PciHeader.
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pub fn from_reader(
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access: &impl ConfigRegionAccess,
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addr: PciAddress,
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) -> Result<PciHeader, PciHeaderError> {
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if unsafe { access.read(addr, 0) } == 0xffffffff {
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return Err(PciHeaderError::NoDevice);
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}
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let header = TyPciHeader::new(addr);
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let (vendor_id, device_id) = header.id(access);
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let (revision, class, subclass, interface) = header.revision_and_class(access);
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let header_type = header.header_type(access);
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let shared = SharedPciHeader {
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full_device_id: FullDeviceId {
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vendor_id,
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device_id,
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class,
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subclass,
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interface,
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revision,
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},
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addr,
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};
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match header_type {
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HeaderType::Endpoint => {
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let endpoint_header = EndpointHeader::from_header(header, access).unwrap();
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let (subsystem_id, subsystem_vendor_id) = endpoint_header.subsystem(access);
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let cap_pointer = (unsafe { access.read(addr, 0x34) } & 0xff) as u8;
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Ok(PciHeader::General(PciEndpointHeader {
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shared,
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subsystem_vendor_id,
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subsystem_id,
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cap_pointer,
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}))
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}
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HeaderType::PciPciBridge => {
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let bridge_header = PciPciBridgeHeader::from_header(header, access).unwrap();
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let secondary_bus_num = bridge_header.secondary_bus_number(access);
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let cap_pointer = (unsafe { access.read(addr, 0x34) } & 0xff) as u8;
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Ok(PciHeader::PciToPci {
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shared,
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secondary_bus_num,
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cap_pointer,
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})
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}
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ty => Err(PciHeaderError::UnknownHeaderType(ty)),
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}
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}
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/// Return all identifying information of the PCI function.
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pub fn full_device_id(&self) -> &FullDeviceId {
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match self {
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PciHeader::General(PciEndpointHeader {
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shared:
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SharedPciHeader {
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full_device_id: device_id,
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..
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},
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..
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})
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| PciHeader::PciToPci {
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shared:
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SharedPciHeader {
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full_device_id: device_id,
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..
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},
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..
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} => device_id,
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}
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}
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/// Return the Vendor ID field.
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pub fn vendor_id(&self) -> u16 {
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self.full_device_id().vendor_id
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}
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/// Return the Device ID field.
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pub fn device_id(&self) -> u16 {
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self.full_device_id().device_id
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}
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/// Return the Revision field.
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pub fn revision(&self) -> u8 {
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self.full_device_id().revision
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}
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/// Return the Interface field.
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pub fn interface(&self) -> u8 {
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self.full_device_id().interface
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}
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/// Return the Subclass field.
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pub fn subclass(&self) -> u8 {
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self.full_device_id().subclass
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}
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/// Return the Class field.
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pub fn class(&self) -> u8 {
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self.full_device_id().class
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}
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}
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impl PciEndpointHeader {
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pub fn endpoint_header(&self, access: &impl ConfigRegionAccess) -> EndpointHeader {
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EndpointHeader::from_header(TyPciHeader::new(self.shared.addr), access).unwrap()
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}
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pub fn full_device_id(&self) -> &FullDeviceId {
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&self.shared.full_device_id
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}
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/// Return the Headers BARs.
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// FIXME use pci_types::Bar instead
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pub fn bars(&self, access: &impl ConfigRegionAccess) -> [PciBar; 6] {
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let endpoint_header = self.endpoint_header(access);
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let mut bars = [PciBar::None; 6];
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let mut skip = false;
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for i in 0..6 {
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if skip {
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skip = false;
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continue;
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}
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match endpoint_header.bar(i, access) {
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Some(TyBar::Io { port }) => {
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bars[i as usize] = PciBar::Port(port.try_into().unwrap())
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}
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Some(TyBar::Memory32 {
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address,
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size,
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prefetchable: _,
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}) => {
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bars[i as usize] = PciBar::Memory32 {
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addr: address,
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size,
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}
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}
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Some(TyBar::Memory64 {
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address,
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size,
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prefetchable: _,
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}) => {
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bars[i as usize] = PciBar::Memory64 {
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addr: address,
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size,
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};
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skip = true; // Each 64bit memory BAR occupies two slots
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}
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None => bars[i as usize] = PciBar::None,
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}
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}
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bars
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}
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pub fn cap_pointer(&self) -> u8 {
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self.cap_pointer
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}
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}
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#[cfg(test)]
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mod test {
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use std::convert::TryInto;
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use pci_types::device_type::DeviceType;
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use pci_types::{ConfigRegionAccess, PciAddress};
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use super::{PciHeader, PciHeaderError};
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struct TestCfgAccess<'a> {
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addr: PciAddress,
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bytes: &'a [u8],
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}
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impl ConfigRegionAccess for TestCfgAccess<'_> {
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fn function_exists(&self, _address: PciAddress) -> bool {
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unreachable!();
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}
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unsafe fn read(&self, addr: PciAddress, offset: u16) -> u32 {
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assert_eq!(addr, self.addr);
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let offset = offset as usize;
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assert!(offset < self.bytes.len());
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u32::from_le_bytes(self.bytes[offset..offset + 4].try_into().unwrap())
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}
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unsafe fn write(&self, _addr: PciAddress, _offset: u16, _value: u32) {
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unreachable!("should not write during tests");
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}
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}
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#[rustfmt::skip]
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const IGB_DEV_BYTES: [u8; 256] = [
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0x86, 0x80, 0x33, 0x15, 0x07, 0x04, 0x10, 0x00, 0x03, 0x00, 0x00, 0x02, 0x10, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x50, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x01, 0xb0, 0x00, 0x00, 0x00, 0x00, 0x58, 0xf7,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd9, 0x15, 0x33, 0x15,
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0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x01, 0x00, 0x00,
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0x01, 0x50, 0x23, 0xc8, 0x08, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x05, 0x70, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x11, 0xa0, 0x04, 0x80, 0x03, 0x00, 0x00, 0x00, 0x03, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
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0x10, 0x00, 0x02, 0x00, 0xc2, 0x8c, 0x00, 0x10, 0x0f, 0x28, 0x19, 0x00, 0x11, 0x5c, 0x42, 0x00,
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0x42, 0x00, 0x11, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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];
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#[test]
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fn tset_parse_igb_dev() {
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let header = PciHeader::from_reader(
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&TestCfgAccess {
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addr: PciAddress::new(0, 2, 4, 0),
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bytes: &IGB_DEV_BYTES,
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},
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PciAddress::new(0, 2, 4, 0),
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)
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.unwrap();
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match header {
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PciHeader::General { .. } => {}
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_ => panic!("wrong header type"),
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}
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assert_eq!(header.device_id(), 0x1533);
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assert_eq!(header.vendor_id(), 0x8086);
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assert_eq!(header.revision(), 3);
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assert_eq!(header.interface(), 0);
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assert_eq!(
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DeviceType::from((header.class(), header.subclass())),
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DeviceType::EthernetController
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);
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assert_eq!(header.subclass(), 0);
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}
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#[test]
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fn test_parse_nonexistent() {
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let bytes = &[0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff];
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assert_eq!(
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PciHeader::from_reader(
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&TestCfgAccess {
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addr: PciAddress::new(0, 2, 4, 0),
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bytes,
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},
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PciAddress::new(0, 2, 4, 0),
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),
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Err(PciHeaderError::NoDevice)
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);
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}
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}
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