4lDO2
105 lines
3.1 KiB
Rust
105 lines
3.1 KiB
Rust
use std::cell::Cell;
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use std::convert::TryFrom;
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use std::sync::Mutex;
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#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
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use syscall::io::{Io as _, Pio};
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use log::info;
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use pci_types::{ConfigRegionAccess, PciAddress};
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pub(crate) struct Pci {
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lock: Mutex<()>,
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}
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impl Pci {
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pub(crate) fn new() -> Self {
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Self {
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lock: Mutex::new(()),
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}
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}
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fn set_iopl() {
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// The IO privilege level is per-thread, so we need to do the initialization on every thread.
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thread_local! {
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static IOPL_ONCE: Cell<bool> = Cell::new(false);
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}
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IOPL_ONCE.with(|iopl_once| {
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if !iopl_once.replace(true) {
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// make sure that pcid is not granted io port permission unless pcie memory-mapped
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// configuration space is not available.
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info!(
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"PCI: couldn't find or access PCIe extended configuration, \
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and thus falling back to PCI 3.0 io ports"
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);
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common::acquire_port_io_rights().expect("pcid: failed to get IO port rights");
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}
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});
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}
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fn address(address: PciAddress, offset: u8) -> u32 {
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assert_eq!(
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address.segment(),
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0,
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"usage of multiple segments requires PCIe extended configuration"
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);
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assert_eq!(offset & 0xFC, offset, "pci offset is not aligned");
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0x80000000
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| (u32::from(address.bus()) << 16)
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| (u32::from(address.device()) << 11)
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| (u32::from(address.function()) << 8)
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| u32::from(offset)
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}
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}
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#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
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impl ConfigRegionAccess for Pci {
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fn function_exists(&self, _address: PciAddress) -> bool {
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todo!();
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}
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unsafe fn read(&self, address: PciAddress, offset: u16) -> u32 {
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let _guard = self.lock.lock().unwrap();
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Self::set_iopl();
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let offset =
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u8::try_from(offset).expect("offset too large for PCI 3.0 configuration space");
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let address = Self::address(address, offset);
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Pio::<u32>::new(0xCF8).write(address);
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Pio::<u32>::new(0xCFC).read()
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}
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unsafe fn write(&self, address: PciAddress, offset: u16, value: u32) {
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let _guard = self.lock.lock().unwrap();
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Self::set_iopl();
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let offset =
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u8::try_from(offset).expect("offset too large for PCI 3.0 configuration space");
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let address = Self::address(address, offset);
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Pio::<u32>::new(0xCF8).write(address);
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Pio::<u32>::new(0xCFC).write(value);
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}
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}
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#[cfg(not(any(target_arch = "x86", target_arch = "x86_64")))]
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impl ConfigRegionAccess for Pci {
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fn function_exists(&self, _address: PciAddress) -> bool {
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todo!();
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}
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unsafe fn read(&self, addr: PciAddress, offset: u16) -> u32 {
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let _guard = self.lock.lock().unwrap();
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todo!("Pci::CfgAccess::read on this architecture")
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}
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unsafe fn write(&self, addr: PciAddress, offset: u16, value: u32) {
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let _guard = self.lock.lock().unwrap();
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todo!("Pci::CfgAccess::write on this architecture")
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}
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}
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