vasilito a9cec3954d intel: VRR + DSC — Variable Refresh Rate and Display Stream Compression ...

vrr.rs: Adaptive Sync / VRR support
  VRR_CTL enable with flip line configuration
  Min/max vtotal frame time programming
  Transcoder-based VRR status monitoring

dsc.rs: DSC 1.2a compression encoder
  PPS (Picture Parameter Set) computation per mode
  Slice count (1/2/4/8) and BPC (8/10/12) configuration
  DPCD sink DSC enable/disable communication
  probe_sink_caps via DP_DSC_SUPPORT register

2026-06-02 06:07:50 +03:00

..

Assets/images

Red Bear OS — microkernel OS in Rust, based on Redox

2026-04-12 19:05:00 +01:00

cache

migrate: finalize source ownership — mini ISO builds and boots

2026-05-30 00:38:25 +03:00

config

Merge bootprocess branch overlay into 0.2.0

2026-05-27 06:47:23 +03:00

docs

intel: fix pre-Gen9 per-gen flags, enable Gen8 PPGTT, expand plan

2026-06-01 22:59:09 +03:00

recipes

intel: VRR + DSC — Variable Refresh Rate and Display Stream Compression

2026-06-02 06:07:50 +03:00

scripts

fix: complete m4 recipe - fix_types.h with all sys types, typedef stripping

2026-06-01 21:03:27 +03:00

sources

fix: bits_pthread cbindgen needs stddef.h for size_t type

2026-06-01 17:00:53 +03:00

AGENTS.md

docs: rewrite local/AGENTS.md for source ownership model

2026-05-29 22:54:38 +03:00