b9874d0941
Add redbear-usb-storage-check in-guest binary that validates USB mass storage read and write I/O: discovers /scheme/disk/ devices, writes a test pattern to sector 2048, reads it back, verifies match, restores original content. Updates test-usb-storage-qemu.sh with write-proof verification step. Includes all accumulated Red Bear OS work: kernel patches, relibc patches, driver infrastructure, DRM/GPU, KDE recipes, firmware, validation tooling, build system hardening, and documentation.
182 lines
6.7 KiB
Rust
182 lines
6.7 KiB
Rust
//! The eXtensible Host Controller Interface (XHCI) Daemon
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//!
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//! This crate provides the executable xhcid daemon that implements the driver for interacting with
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//! a PCIe XHCI device
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//!
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//! XHCI is a standard for the USB Host Controller interface specified by Intel that provides a
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//! common register interface for systems to use to interact with the Universal Serial Bus (USB)
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//! subsystem.
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//!
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//! USB consists of three types of devices: The Host Controller/Root Hub, USB Hubs, and Endpoints.
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//! Endpoints represent actual devices connected to the USB fabric. USB Hubs are intermediaries
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//! between the Host Controller and the endpoints that report when devices have been connected/disconnected.
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//! The Host Controller provides the interface to the USB subsystem that software running on the
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//! system's CPU can interact with. It's a tree-like structure, which the Host Controller enumerating
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//! and addressing all the hubs and endpoints in the tree. Data then flows through the fabric
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//! using the USB protocol (2.0 or 3.2) as packets. Hubs have multiple ports that endpoints can
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//! connect to, and they notify the Host Controller/Root Hub when devices are hot plugged or removed.
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//!
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//! This documentation will refer directly to the relevant standards, which are as follows:
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//!
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//! - XHCI - [eXtensible Host Controller Interface for Universal Serial Bus (xHCI) Requirements Specification](https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf)
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//! - USB2 - [Universal Serial Bus Specification](https://www.usb.org/document-library/usb-20-specification)
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//! - USB32 - [Universal Serial Bus 3.2 Specification Revision 1.1](https://usb.org/document-library/usb-32-revision-11-june-2022)
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//!
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#![allow(warnings)]
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#[macro_use]
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extern crate bitflags;
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use std::fs::File;
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use std::sync::Arc;
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use pcid_interface::irq_helpers::read_bsp_apic_id;
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#[cfg(target_arch = "x86_64")]
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use pcid_interface::irq_helpers::{
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allocate_first_msi_interrupt_on_bsp, allocate_single_interrupt_vector_for_msi,
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};
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use pcid_interface::{PciFeature, PciFeatureInfo, PciFunctionHandle};
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use redox_scheme::{scheme::register_sync_scheme, Socket};
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use scheme_utils::Blocking;
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use crate::xhci::{InterruptMethod, Xhci};
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// Declare as pub so that no warnings appear due to parts of the interface code not being used by
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// the driver. Since there's also a dedicated crate for the driver interface, those warnings don't
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// mean anything.
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pub mod driver_interface;
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mod usb;
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mod xhci;
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#[cfg(target_arch = "x86_64")]
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fn get_int_method(pcid_handle: &mut PciFunctionHandle) -> (Option<File>, InterruptMethod) {
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let pci_config = pcid_handle.config();
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let all_pci_features = pcid_handle.fetch_all_features();
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log::debug!("XHCI PCI FEATURES: {:?}", all_pci_features);
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let has_msi = all_pci_features.iter().any(|feature| feature.is_msi());
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let has_msix = all_pci_features.iter().any(|feature| feature.is_msix());
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if has_msix {
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let msix_info = match pcid_handle.feature_info(PciFeature::MsiX) {
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PciFeatureInfo::Msi(_) => panic!(),
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PciFeatureInfo::MsiX(s) => s,
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};
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let mut info = unsafe { msix_info.map_and_mask_all(pcid_handle) };
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// Allocate one msi vector.
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let method = {
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// primary interrupter
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let k = 0;
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let table_entry_pointer = info.table_entry_pointer(k);
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let destination_id = read_bsp_apic_id().expect("xhcid: failed to read BSP apic id");
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let (msg_addr_and_data, interrupt_handle) =
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allocate_single_interrupt_vector_for_msi(destination_id);
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table_entry_pointer.write_addr_and_data(msg_addr_and_data);
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table_entry_pointer.unmask();
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(Some(interrupt_handle), InterruptMethod::Msi)
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};
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pcid_handle.enable_feature(PciFeature::MsiX);
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log::debug!("Enabled MSI-X");
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method
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} else if has_msi {
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let interrupt_handle = allocate_first_msi_interrupt_on_bsp(pcid_handle);
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(Some(interrupt_handle), InterruptMethod::Msi)
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} else if let Some(irq) = pci_config.func.legacy_interrupt_line {
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log::debug!("Legacy IRQ {}", irq);
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// legacy INTx# interrupt pins.
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(Some(irq.irq_handle("xhcid")), InterruptMethod::Intx)
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} else {
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// no interrupts at all
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(None, InterruptMethod::Polling)
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}
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}
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//TODO: MSI on non-x86_64?
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#[cfg(not(target_arch = "x86_64"))]
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fn get_int_method(pcid_handle: &mut PciFunctionHandle) -> (Option<File>, InterruptMethod) {
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let pci_config = pcid_handle.config();
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if let Some(irq) = pci_config.func.legacy_interrupt_line {
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// legacy INTx# interrupt pins.
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(Some(irq.irq_handle("xhcid")), InterruptMethod::Intx)
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} else {
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// no interrupts at all
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(None, InterruptMethod::Polling)
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}
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}
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//TODO: cleanup CSZ support
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fn daemon_with_context_size<const N: usize>(
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daemon: daemon::Daemon,
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mut pcid_handle: PciFunctionHandle,
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) -> ! {
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let pci_config = pcid_handle.config();
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let mut name = pci_config.func.name();
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name.push_str("_xhci");
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common::setup_logging(
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"usb",
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"host",
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&name,
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common::output_level(),
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common::file_level(),
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);
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log::debug!("XHCI PCI CONFIG: {:?}", pci_config);
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let address = unsafe { pcid_handle.map_bar(0) }.ptr.as_ptr() as usize;
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let (irq_file, interrupt_method) = (None, InterruptMethod::Polling); //get_int_method(&mut pcid_handle);
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//TODO: Fix interrupts.
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log::info!("XHCI {}", pci_config.func.display());
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let scheme_name = format!("usb.{}", name);
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let socket = Socket::create().expect("xhcid: failed to create usb scheme");
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let handler = Blocking::new(&socket, 16);
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let hci = Arc::new(
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Xhci::<N>::new(scheme_name.clone(), address, interrupt_method, pcid_handle)
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.expect("xhcid: failed to allocate device"),
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);
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register_sync_scheme(&socket, &scheme_name, &mut &*hci)
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.expect("xhcid: failed to regsiter scheme to namespace");
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daemon.ready();
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xhci::start_irq_reactor(&hci, irq_file);
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xhci::start_device_enumerator(&hci);
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hci.poll();
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handler
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.process_requests_blocking(&*hci)
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.expect("xhcid: failed to process requests");
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}
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fn main() {
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pcid_interface::pci_daemon(daemon);
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}
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fn daemon(daemon: daemon::Daemon, mut pcid_handle: PciFunctionHandle) -> ! {
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let address = unsafe { pcid_handle.map_bar(0) }.ptr.as_ptr() as usize;
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let cap = unsafe { &mut *(address as *mut xhci::CapabilityRegs) };
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if cap.csz() {
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daemon_with_context_size::<{ xhci::CONTEXT_64 }>(daemon, pcid_handle)
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} else {
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daemon_with_context_size::<{ xhci::CONTEXT_32 }>(daemon, pcid_handle)
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}
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}
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