Files
RedBear-OS/local
vasilito a52ffc5ac6 intel: color pipeline, DMC DC5/6, PSR full, GuC submission — remaining MAJOR
color_pipeline.rs: CSC/CTM coefficient encoding with precision
  encode_csc_coefficient: 12-bit fixed point with sign bit
  encode_ctm_coefficient: 64-bit FP with mantissa + exponent
  compute_hdr_metadata: ST.2086 HDR static metadata block
  ColorPipelineState struct (degamma/CSC/CTM/gamma enables)

dmc_power.rs: DC5/DC6 deep power states
  allow_dc5/allow_dc6 with DMC firmware handshake
  disallow_dc5/disallow_dc6 for display active prevention
  DC state register controls at 0x45400/0x45404/0x45504

psr_full.rs: complete PSR sink+source communication
  DPCD PSR_STATUS/ERROR_STATUS/SINK_STATUS monitoring
  PSR exit request via sink DPCD write
  Source PSR state polling (SRDENT/SRDONACK/IDLE)
  Error/entry/exit counter tracking

guc_submission.rs: GuC work queue submission protocol
  WQ head/tail ring buffer management
  doorbell trigger with per-context ID assignment
  CT message: context register/deregister, sched policy
  Timeslice + preemption timeout configuration
2026-06-02 06:19:57 +03:00
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